Metal Insulator Semiconductor Research Articles

Exploration of microstructural, chemical states and electrical features of the Au/Er2O3/n-GaN MIS diode with a Er2O3 interlayer

The study involved the formation of high-k erbium oxide (Er2O3) films on the n-GaN surface and evaluated their microstructural and chemical states by XRD, TEM and XPS approaches. By employing Er2O3 as an interlayer between the Au and n-GaN substrate, the metal/insulator/ semiconductor (MIS) diode is developed and explored its electrical features by I–V and C–V procedures. The electrical properties of the MIS diode demonstrate a better rectification nature with a lower leakage current compared with the Au/n-GaN Schottky diode (SD). The MIS diode's derived barrier height (BH) is higher than the SD, suggesting that Er2O3 plays a momentous role in altering the BH. The BH was determined using Cheung’s and Norde techniques, and the measurements showed a high degree of consistency, indicating the methods used are valid. The derived density of states (NSS) value for the MIS diode is beneath the SD, suggesting that the Er2O3 layer significantly contributes to the reduction of NSS. Under reverse bias, the PFE is a dominant current mechanism in the lower-bias, whereas the SE is the leading current mechanism in the higher-bias region of the SD. However, the PFE is the prevailing conduction mechanism in the lower-bias and higher-bias regions of the MIS diode. Outcomes of the investigation reveal that the Er2O3 thin films are favorable interfacial layers for fabricating MIS/MOS diodes.

Analog Synaptic Devices Based on IGZO Thin‐Film Transistors with a Metal–Ferroelectric–Metal–Insulator–Semiconductor Structure for High‐Performance Neuromorphic Systems

A ferroelectric thin‐film transistor (FeTFT)‐based synaptic device with an indium–gallium–zinc oxide (IGZO) channel and a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure is reported. The fabricated FeTFT exhibits a highly linear conductance response (|α| = 0.21) with a large dynamic range (Gmax/Gmin ≈ 53.2), although identical program pulses are applied to the device. In addition, because the inner metal layer of the FeTFTs has an MFMIS structure, the electric field is uniformly applied to the entire IGZO channel, which reduces the cycle‐to‐cycle variation (σ = 0.47%) in the conductance responses. In the system simulation with the measured synaptic characteristics, the high classification accuracy of ≈97.0% is achieved in the MNIST image set, verifying the feasibility of FeTFT‐based neuromorphic systems.

Two-dimensional tellurium-based diodes for RF applications

The research of two-dimensional (2D) Tellurium (Te) or tellurene is thriving to address current challenges in emerging thin-film electronic and optoelectronic devices. However, the study of 2D-Te-based devices for high-frequency applications is still lacking in the literature. This work presents a comprehensive study of two types of radio frequency (RF) diodes based on 2D-Te flakes and exploits their distinct properties in two RF applications. First, a metal-insulator-semiconductor (MIS) structure is employed as a nonlinear device in a passive RF mixer, where the achieved conversion loss at 2.5 GHz and 5 GHz is as low as 24 dB and 29 dB, respectively. Then, a metal-semiconductor (MS) diode is tested as a zero-bias millimeter-wave power detector and reaches an outstanding linear-in-dB dynamic range over 40 dB, while having voltage responsivities as high as 257 V ⋅ W−1 at 1 GHz (up to 1 V detected output voltage) and 47 V ⋅ W−1 at 2.5 GHz (up to 0.26 V detected output voltage). These results show superior performance compared to other 2D material-based devices in a much more mature technological phase. Thus, the authors believe that this work demonstrates the potential of 2D-Te as a promising material for devices in emerging high-frequency electronics.

MISHEMT intrinsic voltage gain under multiple channel output characteristics

In this paper the MISHEMT device (metal/Si3N4/AlGaN/AlN/GaN - metal–insulator–semiconductor high electron mobility transistor) is studied focusing mainly on the impact of the multiple conductions on the intrinsic voltage gain (A v). It is shown that the total drain current is composed of three different drain current components, whereof one is related to the MIS channel and the other two are related to high electron mobility transistor (HEMT) channels. The device output characteristics present double drain voltage saturation that gives rise to a double plateau in the saturation region of the output characteristics. This behavior relies also on the gate voltage, so the output characteristics and analog parameters extraction are bias dependent. The intrinsic voltage gain increases thanks to the early voltage increment in the second plateau where HEMT conduction is dominant. Electron concentration profiles were simulated in order to investigate the device saturation regime.

Interface charge engineering on an in situ SiNx/AlGaN/GaN platform for normally off GaN MIS-HEMTs with improved breakdown performance

This work adopts interface charge engineering to fabricate normally off metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) on an in situ SiNx/AlGaN/GaN platform using an in situ O3 treatment performed in the atomic layer deposition system. The combination of in situ SiNx passivation and an O3-treated Al2O3/AlGaN gate interface allows the device to provide an excellent breakdown voltage of 1498 V at a low specific on-resistance of 2.02 mΩ cm2. The threshold voltage is increased by 2 V by significantly compensating the net polarization charges by more than five times with O3 treatment as well as reducing the interface traps and improving the high-temperature gate stability. Furthermore, a physical model of fixed charges at the Al2O3/AlGaN interface is established based on dielectric thickness-dependent linear fitting and numerical calculations. The matched device performance and simulated energy band bending elucidate the O3-treated fixed-charge modulation mechanism, providing a practical method for producing normally off GaN MIS-HEMTs.

Disordered plasmonic nanocavity enhanced quantum dot emission

In this paper, a large-scale compatible plasmonic nanocavity design platform is utilized to achieve a nearly order of magnitude photoluminescence (PL) enhancement. The proposed design is made of multi-sized/multi-spacing gold (Au) nanounits that are uniformly wrapped with a thin aluminum oxide (Al2O3) layer, as a foreign host to form a metal–insulator–semiconductor cavity, as they are coated with semiconductor quantum dots (QDs). Our numerical and experimental data demonstrate that, in an optimal insulator layer thickness, the simultaneous formation of broadband Fabry–Perot resonances and plasmonic hot spots leads to enhanced light absorption within the QD unit. This improvement in absorption response leads to the PL enhancement of QDs. This work demonstrates the potential and effectiveness of a random plasmonic nanocavities host in the realization of lithography-free efficient emitters.

(Digital Presentation) Analysis of MIS-HEMT Kink Effect in Saturation Region

The High Electron Mobility Transistor (HEMT) has been widely used in the field of power electronics and high frequency operation since 1983 (1), while presenting a simple circuit design for analog applications (2, 3), and for extreme harsh environments as well (3, 4). However, HEMTs presents a problem with gate leakage and current collapse which can be solved by introducing an insulator between the gate and semiconductor while maintaining the high performance, hence the Metal Insulator Semiconductor High Electron Mobility Transistor (MIS-HEMT) appears as a solution. The AlGaN/GaN heterostructures forms, at the interface, a sheet with high electron density (2DEG – 2 Dimension Electron Gas), which also presents a high electron mobility. The MIS structure presents a well know conduction between source and drain. As a result, the MIS-HEMT device presents multiple conductions. The focus of this work is to study how the multiple conductions of the MIS-HEMT impact on the output characteristics.The studied devices are, a MIS-HEMT with the gate insulator composed of a 2 nm Si3N4, and a GaN MOSFET of 25 nm of Al2O3 as the gate insulator, both devices were fabricated at imec Leuven – Belgium, and have the same dimensions: gate width of 5 µm and gate length of 600 nm. Their respective schematics are presented at figure 1.The drain current (IDS) as a function of drain voltage (VDS) for a MIS-HEMT (left) and GaN MOSFET (right) with multiple overdrive voltage (VGT) is presented in figure 2. The VDS ranges for these devices are different because they have different saturation points, although it is possible to notice that the MIS-HEMT shows greater current drive when compared to MOSFET considering the same VDS, which is likely due to the formation of the 2DEG as the main conducting mechanism in the MIS-HEMT.Previous works (5 – 8) showed that the MIS-HEMT have multiple conduction mechanisms dependent on VGT, and figure 3 shows the effect of those multiple conductions on the output current of the device where it is very likely that one of those conductions have different VDS sat. It is possible to notice higher values of IDS with increasing VGT, as expected. However, for high enough VGT, there is an anomalous IDS increase (kink) in the saturation region, that occurs due to the different conduction mechanism (MOS and HEMT conductions). This effect will be called as MIS-HEMT kink effect (MH kink effect). This MH Kink effect occurs when the HEMT conduction mechanism overcomes the MOS conduction.The output conductance (gD) as a function of VDS for the MOSFET is presented in figure 4. Figure 5 shows gD as a function of VDS for multiple VGT for the MIS-HEMT, where it is possible to see a peak in the gD (in saturation region) shifting to the right for increasing VGT, caused by the MH kink effect.In order to better visualize, the VDS value for which the MH kink takes place, it is plotted as a function of VGT in figure 6. It is possible to see that as VGT increases, the MK kink effect shifts for higher VDS values, thanks to the higher electron density in 2DEG making the HEMT conduction less dependent on VDS. Figure 1

A novel plasmonic metal–semiconductor–insulator–metal (MSIM) color sensor compatible with CMOS technology

Color detection is one of the top interests in both biological and industrial applications. Specifically, the Determination of the light wave characteristics is vital in photonic technology. One of the features in the color sense that should be found out is its wavelength or color. In this work, we propose a structure that can be used to detect RGB colors separately in an efficient way. The proposed detector consists of the plasmonic filter sensing desired wavelength (red, green, and blue) and the PN diode to convert the received photons to the electrical current. At the input intensity of 1 mW × cm−2, the current density for blue, green, and red colors are 27, 35, and 48 µA × cm−2, respectively. It is shown that the intensities needed to obtain the current densities of 0.1 µA × cm−2 are 3.94, 2.98, and 2.25 µW × cm−2 for the blue, green, and red spectra respectively. It should mention that by using high-precision photodetector structures such as PIN diode, the minimum detectable level can be decreased. Simple adjusting for desired wavelength and linear operation for different input intensities are the characteristics of the designed structure. This detector is compatible with CMOS technology and can be easily utilized in numerous applications, such as charge-coupled devices, displays, and cameras.

Exploring the Physical Origin of the Negative Capacitance Effect in a Metal–Ferroelectric–Metal–Dielectric Structure

AbstractThe ferroelectric negative capacitance (NC) draws a great deal of attention for low‐power negative capacitance field‐effect transistors (NCFET) and NC capacitors. The fabrication of steep‐slope FET (subthreshold swing < 60mVdec−1) is reported, followed by modeling approaches. While the device fabrication favors a ferroelectric gate structure without interlayer metal, many NCFET models adopt interlayer metal between the ferroelectric layer and metal–insulator–semiconductor structure. The metal interlayer averages out spatial variation in the ferroelectric polarization, enabling a compact charge‐based relation between the layers. In addition, the approach assumes that the NC effect emerges from the ferroelectric layer regardless of the metal interlayer, which is not necessarily probable. This work reinvestigates the possible NC effect in ferroelectric–dielectric capacitors connected by a metal interlayer. The experiment confirms that the NC effect in the metal–ferroelectric–dielectric–metal structure does not appear in the metal–ferroelectric–metal–dielectric–metal structure. These results are inconsistent with the multidomain‐1D Landau–Ginzburg‐Devonshire model. In contrast, the suppression of the NC effect in the structure is fully explained by the advanced inhomogeneous stray‐field energy model, which simulates the dynamic evolution of polarization and screening charges. Therefore, an NCFET with a metal interlayer is impractical.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

Design and Fabrication of Room Temperature Electrically Pumped ZnO Nanowire Hybrid Plasmonic Lasers

Plasmonic lasers have attracted much attention because they can break through the diffraction limit, but due to the large metal loss limitations, electrically driven plasmonic lasers mainly work at low temperatures to achieve sufficient gain. Therefore, we proposed electrically pumped nanowire plasmonic lasers at room temperature. Here, the metal/insulator/semiconductor (MIS) structure was applied to reduce the metal loss by separating the active area and the metal layer through the insulator. We illustrate the superiority of plasmonic laser performance by comparing plasmonic and photon lasers at room temperature. Our research provides some experimental basis for the realization of future optoelectronic integration.

Light-triggered 2D electron gas in a GaN-based HEMT with sandwiched p-GaN layers.

In this work, a p-n junction-coupled metal-insulator-semiconductor (MIS) normally-off high-electron-mobility transistor (HEMT) UVPD is proposed. A two-dimensional electron gas (2DEG) at the AlN/U-GaN interface is entirely depleted with a dark current of 1.97 × 10-11 A because of the design of the sandwiched p-GaN layers. Under 365 nm illumination, the 2DEG is light triggered at Vds = 1 V with a high light on/off ratio of over 107 at a light power density of 286.39 mW·cm-2. Meanwhile, it exhibits fast rise and decay times of 248.39 and 584.79 µs, respectively. Moreover, a maximum responsivity (R) of 2.33 A/W, a maximum EQE of 793%, and a D* of 1.08 × 1013 Jones are obtained at Vds = 1 V. This can be attributed to the built-in electric fields in the configuration, which accelerate the flow of photogenerated carriers into the AlN/U-GaN channel. Additionally, the device showcases stable durability, repeatability, and a low driving voltage, making it highly suitable for applications in UV communication and space exploration.

Overcoming the Fermi-Level Pinning Effect in the Nanoscale Metal and Silicon Interface.

Silicon-based photodetectors are attractive as low-cost and environmentally friendly optical sensors. Also, their compatibility with complementary metal-oxide-semiconductor (CMOS) technology is advantageous for the development of silicon photonics systems. However, extending optical responsivity of silicon-based photodetectors to the mid-infrared (mid-IR) wavelength range remains challenging. In developing mid-IR infrared Schottky detectors, nanoscale metals are critical. Nonetheless, one key factor is the Fermi-level pinning effect at the metal/silicon interface and the presence of metal-induced gap states (MIGS). Here, we demonstrate the utilization of the passivated surface layer on semiconductor materials as an insulating material in metal-insulator-semiconductor (MIS) contacts to mitigate the Fermi-level pinning effect. The removal of Fermi-level pinning effectively reduces the Schottky barrier height by 12.5% to 16%. The demonstrated devices exhibit a high responsivity of up to 234 μA/W at a wavelength of 2 μm, 48.2 μA/W at 3 μm, and 1.75 μA/W at 6 μm. The corresponding detectivities at 2 and 3 μm are 1.17 × 108 cm Hz1/2 W-1 and 2.41 × 107 cm Hz1/2 W-1, respectively. The expanded sensing wavelength range contributes to the application development of future silicon photonics integration platforms.

2D Amorphous GaOX Gate Dielectric for β-Ga2O3 Field-Effect Transistors.

Appropriate gate dielectrics must be identified to fabricate metal-insulator-semiconductor field-effect transistors (MISFETs); however, this has been challenging for compound semiconductors owing to the absence of high-quality native oxides. This study uses the liquid-gallium squeezing technique to fabricate 2D amorphous gallium oxide (GaOX) with a high dielectric constant, where its thickness is precisely controlled at the atomic scale (monolayer, ∼4.5 nm; bilayer, ∼8.5 nm). Beta-phase gallium oxide (β-Ga2O3) with an ultrawide energy bandgap (4.5-4.9 eV) has emerged as a next-generation power semiconductor material and is presented here as the channel material. The 2D amorphous GaOX dielectric is combined with a β-Ga2O3 conducting nanolayer, and the resulting β-Ga2O3 MISFET is stable up to 250 °C. The 2D amorphous GaOX is oxygen-deficient, and a high-quality interface with excellent uniformity and scalability forms between the 2D amorphous GaOX and β-Ga2O3. The fabricated MISFET exhibits a wide gate-voltage swing of approximately +5 V, a high current on/off ratio, moderate field-effect carrier mobility, and a decent three-terminal breakdown voltage (∼138 V). The carrier transport of the Ni/GaOX/β-Ga2O3 metal-insulator-semiconductor (MIS) structure displays a combination of Schottky emission and Fowler-Nordheim (F-N) tunneling in the high-gate-bias region at 25 °C, whereas at elevated temperatures it shows Schottky emission and F-N tunneling in the low- and high-gate-bias regions, respectively. This study demonstrates that a 2D GaOX gate dielectric layer can be produced and incorporated into an active channel layer to form an MIS structure at room temperature (∼25 °C), which enables the facile fabrication of MISFET devices.

Interplay of Precursor and Plasma for The Deposition of HfO2 via PEALD: Film Growth and Dielectric Properties

AbstractHfO2 thin films are appealing for microelectronic applications such as high‐κ dielectric layers, memristors, and ferroelectric memory devices. To fulfill the different requirements of each application, the properties of the deposited material need to be tuned accordingly. In this context, plasma‐enhanced atomic layer deposition (PEALD) is a powerful processing route to tailor the properties of HfO2 thin films, especially at low temperatures. Herein, a comprehensive bottom‐up approach is presented, ranging from the synthesis of molecularly engineered Hf precursors to the development of a HfO2 PEALD process and a detailed evaluation where plasma can be exploited to tune the dielectric properties. With the example of the newly synthesized bis‐(dialkylamido)‐bis‐(formamidinato) Hf(IV) precursor, [Hf{η2‐(iPrN)2CH}2(NMe2)2] which is reactive, thermally robust and volatile, successful implementation in a PEALD process for HfO2 at low temperatures is demonstrated. The typical atomic layer deposition (ALD) characteristics of precursor saturation, linearity, and ALD temperature window are demonstrated with constant growth of 0.7 Å per cycle from 125 to 200 °C, yielding high‐purity layers. The effect of plasma pulse duration on the chemical composition alongside structural, topographical, as well as dielectric properties of the films is investigated. For the latter, the films are incorporated in metal‐insulator semiconductor (MIS) structures.

Analytical model and simulation study of a novel enhancement-mode Ga2O3 MISFET realized by p-GaN gate

In this paper, we propose a novel junction-less Ga2O3 metal–insulator–semiconductor field effect transistor (MISFET) with a p-GaN gate, named p-GaN Ga2O3-MISFET. A heavily doped thin layer p-GaN is set in the trench gate region to deeply deplete the n-Ga2O3 channel region owing to the high work function of the p-GaN. Thus, a high threshold voltage (V TH) and breakdown voltage (BV) can be obtained even with a wide-fin design and low interface charge density (n int), which ensures easy fabrication and a stable V TH. Analytical modeling and experimentally calibrated technology computer aided design (TCAD) simulations confirm that with the increase of fin width (W Fin) from 0.1 μm to 0.5 μm, the V TH of the p-GaN Ga2O3-MISFET varies from 3.2 V to 2.4 V with n int = −1 × 1011 cm−2, which is always about 2.2 V higher than those of conventional junction-less Ga2O3 MISFETs (CJL-MISFET). In addition, the BV of the CJL-MISFET decreases from ∼3400 V to ∼45 V with increasing W Fin due to soft breakdown, while the BV of the p-GaN MISFET only decreases to 2800 V due to the enhanced electric field at the corner of the trench gate. Moreover, the activation energy and doping concentration (when larger than 3 × 1019 cm−3) of p-GaN barely affect the V TH. Even so, a high V TH remained in a common range of interface charge (from 1 × 1013 cm−2 to 2 × 1013 cm−2) at the p-GaN/Al2O3 interface.

A 35 V–5 V monolithic integrated GaN-based DC–DC floating buck converter

The paper presents the development of a GaN DC–DC power converter with a pre-driver module and power device based on a monolithic integrated GaN E/D-mode metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) platform. The pre-driver module with direct coupled field effect transistor logic circuit structure has been monolithically integrated with a GaN power transistor on a Si-based AlGaN/GaN commercial epitaxial wafer. The MIS-HEMTs structure adopts an insulated gate dielectric layer to suppress the leakage current and increase gate voltage robustness. The GaN-based floating buck converter employs a 1 mH inductor and a 9 μF capacitor to achieve 35 V–5 V power conversion. As a result, the pre-driver module is capable of delivering a 10 V driving voltage. GaN monolithic integration of the pre-driver module and power device can reduce the system area in the DC–DC application, which allows for an integrated chip size of 1.8 mm2.

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Analytical modeling and quasi-static characterization of a lithium niobate (LiNbO3)-based metal–ferroelectric–metal–insulator–semiconductor (MFMIS) NCFET

Vertical metal–dielectric–semiconductor diode on (001) β-Ga2O3 with high-κ TiO2 interlayer exhibiting reduced turn-on voltage and leakage current and improved breakdown

We demonstrate vertical Pt/TiO2/β-Ga2O3 metal–dielectric–semiconductor (MDS) diodes and compare performance with co-fabricated Pt/β-Ga2O3 Schottky diodes (SBDs). The MDS diode exhibits a lower turn-on voltage and leakage current. In addition, the breakdown voltage increased from 548 V for an SBD to 1380 V for a MDS diode. The improvement in the off-state characteristics compared to a SBD while simultaneously reducing on-state losses leads to lower power dissipation at all duty cycles, indicating the great promise of this device architecture for advancing low-loss β-Ga2O3 rectifiers toward material limits.

High Current Density and Low Ron Quaternary InAlGaN MIS-HEMT on Si for Power Applications

In this work, a quaternary In0.04Al0.63Ga0.33N/GaN metal-insulator-semiconductor (MIS)-high electron mobility transistor (HEMT) on Si substrate using a GaN:C back-barrier (BB) layer and an AlGaN/AlN superlattice (SL) buffer layer to achieve a high breakdown voltage and a high output current density was demonstrated. Compared to the conventional device adopting AlGaN as the barrier layer, the proposed device showed a better 2DEG carrier density up to 1.9 × 1013 cm−3, a higher output current density up to 1,070 mA mm−1 (improved by 47%), an on-resistance (Ron) as low as 7.64 Ω mm (decreased by 26%), an off-state breakdown voltage up to 2,070 V, and an improved dynamic Ron performance (dynamic to static ratio increased to just 1.2 times at an applied drain-to-source stress voltage (VDS,stress) of 400 V). These results indicated the great potential of the InAlGaN/GaN MIS-HEMTs on Si for high-power switching applications.