Metal-insulator-semiconductor High-electron-mobility Transistors Research Articles

Control of Surface Chemistry in Recess Etching toward Normally Off GaN Metal–Insulator–Semiconductor High‐Electron‐Mobility Transistors

Reducing off‐state and gate leakage current is crucial in the development of metal–insulator–semiconductor high‐electron‐mobility transistors (MIS‐HEMTs). This work reports interface engineering in the gate recess region through low‐damage digital etching during the fabrication of normally off GaN MIS‐HEMTs. Conventional plasma etching leads to a reduction of the N/(Al+Ga) ratio, but this value recovers to almost 1 with optimized oxidation condition during digital etching, suggesting a reduction of the Al/Ga dangling bonds based on the proposed technique. GaN MIS‐HEMTs with digital etching exhibits a threshold voltage of 1.0 V at 1 μA mm−1, a high ON/OFF current ratio of 1010, a gate breakdown voltage of 22 V, and a low gate leakage current of 10−8 mA mm−1.

Enhanced Breakdown Voltage of AlGaN/GaN MISHEMT using GaN Buffer with Carbon-Doping on Silicon for Power Device

In recent years, Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) have attracted interest in high-power and high-frequency applications. The breakdown mechanism in E-mode GaN MISHEMTs with carbon doping in the GaN buffer grown on a Silicon (Si) substrate (Sub) was investigated using technology computer-aided design simulations. Results showed that GaN MISHEMTs without Si Sub had a breakdown voltage (BV) of 600 V. However, after adding Si Sub to the GaN buffer layer, the electric field (EF) increased, creating a vertical breakdown through the total buffer thickness, therefore, BV was reduced to around 240 V. On the other hand, BV is increased to approximately >1100 V, and the Electric field is reduced after employing a carbon deep acceptor with the proper doping concentration in this device. The GaN MISHEMTs with Si Sub is presented as threshold voltage +1.5 V with transconductance of 700 mS/mm, which is an excellent result compared to GaN MISHEMTs without Si Sub. Eventually, the study device depicted higher BV performance compared to other C-doped GaN HEMT devices. This suggests that the designed GaN MISHEMTs device could effectively be used in power semiconductor devices with optimum performance.

Using U-Net convolutional neural network to model pixel-based electrostatic potential distributions in GaN power MIS-HEMTs

This study demonstrates a novel use of the U-Net convolutional neural network (CNN) for modeling pixel-based electrostatic potential distributions in GaN metal–insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with various gate and source field plate designs and drain voltages. The pixel-based images of the potential distribution are successfully modeled from the developed U-Net CNN with an error of less than 1% error relative to a TCAD simulated reference of a 500-V electrostatic potential distribution in the AlGaN/GaN interface. Furthermore, the modeling time of potential distributions by U-Net takes about 80 ms. Therefore, the U-Net CNN is a promising approach to efficiently model the pixel-based distributions characteristics in GaN power devices.

Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.

Non-equilibrium thermal transport study in steady state GaN MISHEMT channel layer based on electron Monte Carlo and phonon BTE

An electro-thermal coupling simulator for GaN devices based on electron Monte Carlo (e-MC) simulations is established. Taking GaN Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) as example, the non-equilibrium thermal transport processes of self-heating effect in the channel layer are studied. This simulator is mainly coupled by e-MC and the phonon Boltzmann transport equation (pBTE), physical property parameters and electric field parameters are provided by first-principles and Technology Computer Aided Design (TCAD), respectively. We first verify the e-MC program by calculating the electron transport properties of GaN materials, verify the feasibility of the established GaN MISHEMT model by using TCAD and obtained its operating characteristics. Further, the simulator is used to evaluate the non-equilibrium processes inside the channel layer in detail, the results show that there is significant consistency in the peak positions of electric field strength, heat generation and diffusion temperature, the diffusion temperature peak occurs at the secondary peak of heat generation. The frequency distribution of phonon emission under different drain-source bias voltages is revealed by phonon emission spectrum analysis. The strength of the non-equilibrium effect is measured by effective temperature. Increasing the drain-source bias voltage will significantly increase the peak temperature of hotspot and further enhance the non-equilibrium effect. Our study reports an efficient scheme for electro-thermal simulations of GaN MISHEMT, which provides insights for thermal management of GaN-based transistor devices.

Effect of Ultra‐Thin AlGaN Regrown Layer on the Electrical Properties of ZrO2/AlGaN/GaN Structures

Effects of the ultrathin 1 nm thick AlGaN regrown layer before gate insulator deposition on the performance of ZrO2/AlGaN/GaN metal‐insulator‐semiconductor (MIS) structures are investigated. In comparison with the reference ZrO2/AlGaN/GaN MIS high‐electron‐mobility transistors (MIS‐HEMTs), MIS‐HEMTs with AlGaN regrown layer exhibit increased maximum drain current (>1050 mA mm−1) and broader full‐width at half maximum (FWHM) of transconductance profile (11 V). Moreover, the gate leakage current in the forward direction is reduced by about four orders of magnitude while the hysteresis of the transfer curves is cut‐down to more than 40%. Compared with the control MIS‐capacitors (MIS‐caps), MIS‐caps with regrowth show highly evident sudden increase in capacitance known as “spill‐over” in the capacitance–voltage (C–V) profiles, suggesting improved ZrO2/AlGaN interfaces. Extracted electron states from the C–V profiles, reveal 6 times to 14 times reduction of interface states density within 0.2 to 0.8 eV from the AlGaN conduction band edge. Using photo‐assisted C–V measurements, the near mid‐gap electron states density of MIS‐caps is extracted with regrowth to be at least three times less than those of reference MIS‐caps. Findings in this work are very similar to those recently reported Al2O3/regrown‐AlGaN interfaces, suggesting that the regrowth technique could be universal in reducing electron states along insulator/AlGaN interfaces.

Improved breakdown performance in recessed-gate normally off GaN MIS-HEMTs by regrown fishbone trench

This work develops a regrown fishbone trench (RFT) structure in selective area growth (SAG) technique to fabricate recessed-gate normally off GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs). The RFT structure effectively modulates the electric field at high drain and gate biases, thus allowing the device to feature improved off-state and gate breakdown performance with a high positive Vth of 2 V. The simulated carrier concentration and electric field distributions reveal the mechanism of electric field weakening by RFT architecture. Meanwhile, the current collapse phenomenon is significantly suppressed, and the gate voltage swing is also enlarged. The maximum gate drive voltage of 9.2 V for 10-year reliability of RFT GaN MIS-HEMT, together with the improved linearity and block voltage, broadens the applications of SAG devices. Furthermore, the RFT structure also provides an etching-free method for fabricating normally off GaN MIS-HEMTs with multi-dimensional gates.

Improved Vth Stability and Gate Reliability of GaN-Based MIS-HEMTs by Employing Alternating O2 Plasma Treatment.

The Vth stability and gate reliability of AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with alternating O2 plasma treatment were systematically investigated in this article. It was found that the conduction band offset at the Al2O3/AlGaN interface was elevated to 2.4 eV, which contributed to the suppressed gate leakage current. The time-dependent dielectric breakdown (TDDB) test results showed that the ALD-Al2O3 with the alternating O2 plasma treatment had better quality and reliability. The AlGaN/GaN MIS-HEMT with the alternating O2 plasma treatment demonstrated remarkable advantages in higher Vth stability under high-temperature and long-term gate bias stress.

High-Performance N-Polar GaN/AlGaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors with Low Surface Roughness Enabled by Chemical–Mechanical-Polishing-Incorporated Layer Transfer Technology

High-Performance N-Polar GaN/AlGaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistors with Low Surface Roughness Enabled by Chemical–Mechanical-Polishing-Incorporated Layer Transfer Technology

A Comparative Study on the Degradation Behaviors of Ferroelectric Gate GaN HEMT with PZT and PZT/Al2O3 Gate Stacks.

In this paper, the degradation behaviors of the ferroelectric gate Gallium nitride (GaN) high electron mobility transistor (HEMT) under positive gate bias stress are discussed. Devices with a gate dielectric that consists of pure Pb(Zr,Ti)O3 (PZT) and a composite PZT/Al2O3 bilayer are studied. Two different mechanisms, charge trapping and generation of traps, both contribute to the degradation. We have observed positive threshold voltage shift in both kinds of devices under positive gate bias stress. In the devices with a PZT gate oxide, we have found the degradation is owing to electron trapping in pre-existing oxide traps. However, the degradation is caused by electron trapping in pre-existing oxide traps and the generation of traps for the devices with a composite PZT/Al2O3 gate oxide. Owing to the large difference in dielectric constants between PZT and Al2O3, the strong electric field in the Al2O3 interlayer makes PZT/Al2O3 GaN HEMT easier to degrade. In addition, the ferroelectricity in PZT enhances the electric field in Al2O3 interlayer and leads to more severe degradation. According to this study, it is worth noting that the reliability problem of the ferroelectric gate GaN HEMT may be more severe than the conventional metal-insulator-semiconductor HEMT (MIS-HEMT).

Effective suppression of interface states in recessed-gate MIS-HEMTs by TMAH wet etching

The effect of tetramethylammonium hydroxide (TMAH) treatment prior to gate dielectric deposition on the performance of recessed-gate AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) was investigated. Through the use of TMAH wet etching, a low roughness etched surface of 0.173 nm was obtained. The capacitance–voltage characteristics of MIS heterostructures showed that the interface states reduced by one order of magnitude. When the temperature was increased to 473 K, the treated MIS-HEMTs delivered a small threshold voltage shift (ΔV TH) of ∼−0.53 V. From the dynamic measurement, the ΔV TH obtained without treatment was observed more severely (∼−1 V) when compared to the treated one (∼−0.01 V).

Analysis of Operational Characteristics of AlGaN/GaN MIS-HEMT with Different Slant-Recessed-Gate Structures

Purpose of WorkRecessed-gate metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) have emerged as a promising technology for normally-off operation because of their ability to withstand high gate voltage sweeps while maintaining low levels of leakage current [1, 2]. Despite their excellent performance, the etch to leave nanometer-thin layers of AlGaN has proven to be a significant challenge due to difficulties in precisely controlling the etching process. Achieving a positive threshold voltage (Vth) while maintaining the high electron mobility characteristic of the two-dimensional electron gas (2DEG) requires atom-level etch control. Additionally, conventional dry etching techniques can potentially cause damage, presenting a second challenge [3]. However, atomic layer etching (ALE) offers a promising solution with its potential for low damage, uniformity, and high-resolution depth control [4]. In this work, we not only focus on the ALE process to leave nanometer-thin layers of AlGaN/GaN as recessed-gate structures but also analyze the breakdown voltage characteristics of the slant-recessed gate structure.ApproachNormally-off AlGaN/GaN MIS-HEMT with a recessed gate structure was fabricated on a 6-inch commercial Si substrate by MOCVD. The process involved mesa isolation by ICP-RIE, followed by the formation of the ohmic contact (Ti/Al/Ni/Au) at 825 °C annealing for source and drain metals, and the AlGaN/GaN recessed gate structure using ALE technology by O2/BCl3 multiple cycles of oxidation and etching [5]. After the recessed-gate process, the native oxide and carbon residue were removed by a wet cleaning process and O2 plasma treatment, and then the atom layer deposition (ALD) of about 12 nm thickness Al2O3 high-dielectric layer was also deposited. The backend process included gate field plate, SiNx passivation, and contact opening. Finally, the Ni/Au metal stack was deposited as pad electrodes, as shown in Fig. 1. The specific characteristics of the fabricated recessed MIS-HEMT were Lg of 3 μm, Lgs of 5 μm, Lgd of 10 μm, and Wg of 100 μm.Results and SignificanceIn Figure 2(a) and (b), TEM profiles of the recessed gate structure were presented. Following the ALE process for the recessed gate structure, the remaining thickness of AlGaN was approximately 5.1 nm and 5.6 nm for Slant A and Slant B, respectively. Although the thickness of AlGaN remaining was similar in both cases, the slant angle of the recessed gate structure differed, significantly. Specifically, Slant A had a 65-degree recessed gate structure, while Slant B had a 45-degree recessed gate structure. In order to analyze of operational characteristics of AlGaN/GaN MIS-HEMT with different slant-recessed gate structures (Slant A and Slant B), the three-terminal OFF-state breakdown voltage (BV) was measured, as shown in Fig. 3. Recessed gate MIS-HEMT feature design of Lg/Lgd/Lgd/Wg of 3/5/10/100 μm, and VG of -10 V was used as this BV measured condition. The Slant B structure demonstrated higher breakdown voltage (BV) performance compared to the Slant A structure. Specifically, the Slant B structure exhibited a BV of 470 V at 1 μA/mm and 750 V at 1 mA/mm, while the Slant A structure had a BV of only 70 V at 1 μA/mm and 140 V at 1 mA/mm. The reason for the superior BV performance of the Slant B structure (45-degree recessed gate structure) was attributed to the gradient of the AlGaN profile, which facilitates the thin film deposition process of materials such as Al2O3 and gate metal (Ni/Au). Additionally, the Slant B structure helps to reduce the high electric field effect between the gate and drain, further contributing to its improved BV performance.[1] Y. S. Lin, Y. W. Lain, and S. S. H. Hsu, "AlGaN/GaN HEMTs With Low Leakage Current and High On/Off Current Ratio," IEEE Electron Device Letters, vol. 31, no. 2, pp. 102-104, 2010.[2] Z. Tang et al., "600-V Normally Off SiNx/AlGaN/GaN MIS-HEMT With Large Gate Swing and Low Current Collapse," IEEE Electron Device Letters, vol. 34, no. 11, pp. 1373-1375, 2013.[3] T. H. Hung, P. S. Park, S. Krishnamoorthy, D. N. Nath, and S. Rajan, "Interface Charge Engineering for Enhancement-Mode GaN MISHEMTs," IEEE Electron Device Letters, vol. 35, no. 3, pp. 312-314, 2014.[4] T. Y. Yang et al., "A Normally-Off GaN MIS-HEMT Fabricated Using Atomic Layer Etching to Improve Device Performance Uniformity for High Power Applications," IEEE Electron Device Letters, vol. 43, no. 10, pp. 1629-1632, 2022.[5] I.-H. Hwang, H.-Y. Cha, and K.-S. Seo, "Low-Damage and Self-Limiting (Al)GaN Etching Process through Atomic Layer Etching Using O2 and BCl3 Plasma," Coatings, vol. 11, no. 3, p. 268, 2021. Figure 1

Fabrication and Switching Performance of 8 A–500 V D‐Mode GaN MISHEMTs

In this work, the design, fabrication, static device testing, and double‐pulse switching performance of multi‐finger D‐mode GaN metal–insulator–semiconductor high‐electron‐mobility transistors (MISHEMTs) on silicon are discussed. Utilizing an metal‐organic chemical vapor deposition‐grown GaN high‐electron‐mobility transistors stack with a superlattice buffer, field‐plated devices with a meandering gate geometry and a total gate width of 30 mm are fabricated. Plasma enhanced chemical vapor deposition SiNx is used as the gate dielectric, followed by an optimized bilayer SiNx passivation scheme. Devices with 100 μm gate width have an ON/OFF ratio of ≈108. They are analyzed for dynamic Ron (normalized Ron = 3 at 100 μs) and time‐dependent dielectric breakdown for gate reliability, resulting in a β value of 2.65 from the Weibull plot. Devices with a 30 mm gate width exhibit a maximum ON current of 8 A at zero gate voltage and a three‐terminal breakdown of ≈500 V. The devices are diced, wire‐bonded to a printed circuit board, and a double‐pulsed test is performed for switching transient characterization under clamped inductive load. The OFF‐state and ON‐state energy loss are estimated to be Eon = 14 μJ and EOFF = 27 μJ, respectively, when switched at 5 A, 50 V. In this study, the potential of GaN MISHEMTs with bilayer SiNx passivation for low‐power D‐mode switching applications (5 A, 50 V) is demonstrated.

MISHEMT intrinsic voltage gain under multiple channel output characteristics

In this paper the MISHEMT device (metal/Si3N4/AlGaN/AlN/GaN - metal–insulator–semiconductor high electron mobility transistor) is studied focusing mainly on the impact of the multiple conductions on the intrinsic voltage gain (A v). It is shown that the total drain current is composed of three different drain current components, whereof one is related to the MIS channel and the other two are related to high electron mobility transistor (HEMT) channels. The device output characteristics present double drain voltage saturation that gives rise to a double plateau in the saturation region of the output characteristics. This behavior relies also on the gate voltage, so the output characteristics and analog parameters extraction are bias dependent. The intrinsic voltage gain increases thanks to the early voltage increment in the second plateau where HEMT conduction is dominant. Electron concentration profiles were simulated in order to investigate the device saturation regime.

Interface charge engineering on an in situ SiNx/AlGaN/GaN platform for normally off GaN MIS-HEMTs with improved breakdown performance

This work adopts interface charge engineering to fabricate normally off metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) on an in situ SiNx/AlGaN/GaN platform using an in situ O3 treatment performed in the atomic layer deposition system. The combination of in situ SiNx passivation and an O3-treated Al2O3/AlGaN gate interface allows the device to provide an excellent breakdown voltage of 1498 V at a low specific on-resistance of 2.02 mΩ cm2. The threshold voltage is increased by 2 V by significantly compensating the net polarization charges by more than five times with O3 treatment as well as reducing the interface traps and improving the high-temperature gate stability. Furthermore, a physical model of fixed charges at the Al2O3/AlGaN interface is established based on dielectric thickness-dependent linear fitting and numerical calculations. The matched device performance and simulated energy band bending elucidate the O3-treated fixed-charge modulation mechanism, providing a practical method for producing normally off GaN MIS-HEMTs.

(Digital Presentation) Analysis of MIS-HEMT Kink Effect in Saturation Region

The High Electron Mobility Transistor (HEMT) has been widely used in the field of power electronics and high frequency operation since 1983 (1), while presenting a simple circuit design for analog applications (2, 3), and for extreme harsh environments as well (3, 4). However, HEMTs presents a problem with gate leakage and current collapse which can be solved by introducing an insulator between the gate and semiconductor while maintaining the high performance, hence the Metal Insulator Semiconductor High Electron Mobility Transistor (MIS-HEMT) appears as a solution. The AlGaN/GaN heterostructures forms, at the interface, a sheet with high electron density (2DEG – 2 Dimension Electron Gas), which also presents a high electron mobility. The MIS structure presents a well know conduction between source and drain. As a result, the MIS-HEMT device presents multiple conductions. The focus of this work is to study how the multiple conductions of the MIS-HEMT impact on the output characteristics.The studied devices are, a MIS-HEMT with the gate insulator composed of a 2 nm Si3N4, and a GaN MOSFET of 25 nm of Al2O3 as the gate insulator, both devices were fabricated at imec Leuven – Belgium, and have the same dimensions: gate width of 5 µm and gate length of 600 nm. Their respective schematics are presented at figure 1.The drain current (IDS) as a function of drain voltage (VDS) for a MIS-HEMT (left) and GaN MOSFET (right) with multiple overdrive voltage (VGT) is presented in figure 2. The VDS ranges for these devices are different because they have different saturation points, although it is possible to notice that the MIS-HEMT shows greater current drive when compared to MOSFET considering the same VDS, which is likely due to the formation of the 2DEG as the main conducting mechanism in the MIS-HEMT.Previous works (5 – 8) showed that the MIS-HEMT have multiple conduction mechanisms dependent on VGT, and figure 3 shows the effect of those multiple conductions on the output current of the device where it is very likely that one of those conductions have different VDS sat. It is possible to notice higher values of IDS with increasing VGT, as expected. However, for high enough VGT, there is an anomalous IDS increase (kink) in the saturation region, that occurs due to the different conduction mechanism (MOS and HEMT conductions). This effect will be called as MIS-HEMT kink effect (MH kink effect). This MH Kink effect occurs when the HEMT conduction mechanism overcomes the MOS conduction.The output conductance (gD) as a function of VDS for the MOSFET is presented in figure 4. Figure 5 shows gD as a function of VDS for multiple VGT for the MIS-HEMT, where it is possible to see a peak in the gD (in saturation region) shifting to the right for increasing VGT, caused by the MH kink effect.In order to better visualize, the VDS value for which the MH kink takes place, it is plotted as a function of VGT in figure 6. It is possible to see that as VGT increases, the MK kink effect shifts for higher VDS values, thanks to the higher electron density in 2DEG making the HEMT conduction less dependent on VDS. Figure 1

Improving Performance and Breakdown Voltage in Normally-Off GaN Recessed Gate MIS-HEMTs Using Atomic Layer Etching and Gate Field Plate for High-Power Device Applications.

A typical method for normally-off operation, the metal-insulator-semiconductor-high electron mobility transistor (MIS-HEMT) has been investigated. Among various approaches, gate recessed MIS-HEMT have demonstrated a high gate voltage sweep and low leakage current characteristics. Despite their high performance, obtaining low-damage techniques in gate recess processing has so far proven too challenging. In this letter, we demonstrate a high current density and high breakdown down voltage of a MIS-HEMT with a recessed gate by the low damage gate recessed etching of atomic layer etching (ALE) technology. After the remaining 3.7 nm of the AlGaN recessed gate was formed, the surface roughness (Ra of 0.40 nm) was almost the same as the surface without ALE (no etching) as measured by atomic force microscopy (AFM). Furthermore, the devices demonstrate state-of-the-art characteristics with a competitive maximum drain current of 608 mA/mm at a VG of 6 V and a threshold voltage of +2.0 V. The devices also show an on/off current ratio of 109 and an off-state hard breakdown voltage of 1190 V. The low damage of ALE technology was introduced into the MIS-HEMT with the recessed gate, which effectively reduced trapping states at the interface to obtain the low on-resistance (Ron) of 6.8 Ω·mm and high breakdown voltage performance.

Experimental study of MISHEMT from 450 K down to 200 K for analog applications

This work presents an experimental analysis of Metal-Insulator-Semiconductor High Electron Mobility transistor (MISHEMT) operating in a temperature range from 450 K down to 200 K, focusing on analog applications. The drain current and consequently the saturation transconductance (gmsat) showed to be slightly dependent on gate length. The output conductance (gD) presents a higher dependence with gate length than gmsat for the whole temperature range due to the influence of MOS conduction that is strongly affected by short channel effect. There is also a kink in the behavior of these parameters at 350 K, most likely due to the competition of temperature effects on different conduction mechanisms. The transistors showed a good performance in terms of analog application, where the intrinsic voltage gain (AV) increases from 38 dB (at 200 K) to 43 dB (at 450 K) for 800 nm gate length while the unity gain frequency (fT) decreases from 1.8 GHz (at 200 K) to 800 MHz (at 450 K) for a gate length of 400 nm, which makes MISHEMT a good candidate for analog applications.

A 35 V–5 V monolithic integrated GaN-based DC–DC floating buck converter

The paper presents the development of a GaN DC–DC power converter with a pre-driver module and power device based on a monolithic integrated GaN E/D-mode metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) platform. The pre-driver module with direct coupled field effect transistor logic circuit structure has been monolithically integrated with a GaN power transistor on a Si-based AlGaN/GaN commercial epitaxial wafer. The MIS-HEMTs structure adopts an insulated gate dielectric layer to suppress the leakage current and increase gate voltage robustness. The GaN-based floating buck converter employs a 1 mH inductor and a 9 μF capacitor to achieve 35 V–5 V power conversion. As a result, the pre-driver module is capable of delivering a 10 V driving voltage. GaN monolithic integration of the pre-driver module and power device can reduce the system area in the DC–DC application, which allows for an integrated chip size of 1.8 mm2.

N-Polar GaN HEMTs in a High-Uniformity 100-mm Wafer Process With 43.6% Power-Added Efficiency and 2 W/mm at 94 GHz

We report the fabrication of N-polar GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with a power-added efficiency (PAE) of 43.7% from an 8-V supply measured by load pull at 94 GHz. The devices are fabricated on 100-mm SiC substrates and exhibit excellent uniformity, constituting the first report on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$W$</tex-math> </inline-formula> -band power performance across a 100-mm N-polar GaN sample. Compared with the available efficiency of N-polar GaN on SiC at 94 GHz, the devices presented here demonstrate among the highest PAE performance, while delivering a power density of 2 W/mm, competitive with highly scaled, and previously reported both Ga and N-polar devices using an 8-V power supply.