Metal-insulator-semiconductor Devices Research Articles

Structure−Performance Correlations in Vapor Phase Deposited Self-Assembled Nanodielectrics for Organic Field-Effect Transistors

Organic field-effect transistor (OFETs) are fabricated using thin, vapor-deposited films of both the gate dielectric (vapor-deposited self-assembled nanodielectric, v-SAND) and the organic semiconductor. The nanoscopic self-assembled gate dielectrics are structurally organized via molecular precursor hydrogen-bonding interactions, followed by planarization with a vapor-deposited inorganic SiO(x) film. It is shown here that the metal-insulator-semiconductor (MIS) and OFET device electrical properties are sensitive to the v-SAND molecular dipolar orientation. In addition, alternating (organic/inorganic/organic/...) and nonalternating (1 organic layer + 1 inorganic layer) v-SAND microstructural arrangements are investigated, and the microstructures are correlated with MIS and OFET device characteristics. Films with alternating microstructures have larger capacitances than nonalternating films of the same thickness. However, they also have larger leakage currents, associated with the enhanced polarization of well-ordered dipolar films. For pentacene OFETs, the largest mobilities (approximately 3 cm(2)/(V s)) are associated with the high-capacitance nonalternating microstructure, and the lowest mobilities (approximately 0.5 cm(2)/(V s)) are associated with the alternating microstructure. v-SAND gated ambient-stable, n-type organic semiconductors show the opposite trends, where slightly greater OFET performance is observed with the lower-capacitance gate dielectric. For the p-type and one of the n-type v-SAND-based OFETs, the performance (under vacuum and ambient) is comparable to, or surpasses, that of previously reported devices using conventional SiO(2) as the gate dielectric. More importantly, the devices fabricated here operate at far lower voltages. These results indicate that v-SAND dielectrics are promising for future flexible organic electronics requiring low-temperature, solvent-free deposition conditions.

Charge Storage in Pentacene/Polymethylmethacrylate Memory Devices

The electrical behavior of organic metal-insulator-semiconductor (MIS) structures incorporating a layer of self-assembled metallic nanoparticles is described. These have been based on thermally evaporated pentacene (semiconductor) and spin-coated polymethylmethacrylate (insulator). The MIS devices containing the nanoparticles exhibited significant hysteresis in their capacitance-versus-voltage and conductance-versus-voltage characteristics, which was attributed to the charging and discharging of the nanoparticles. The memory structure reported here offers a useful advance in the development of flexible organic memory structures.

Hybrid organic–inorganic materials for molecular proton memory devices

Molecular storage elements consisting of a stack of a proton conducting layer (PCL) and a proton trapping layer (PTL) are investigated in view of their perspective application to non-volatile proton memories. Experimental studies are conducted on PCL and PTL materials made of poly(methyl methacrylate) (PMMA) with embedded molecules of 12-tungstophosphoric acid (HPW) and 2-aminoanthracene (AA), respectively. Particular emphasis is placed on the thermal processing parameters (temperature and duration) used in material preparation and their optimization for circumventing undesirable phenomena, for the device stability and performance, like reactions between HPW and PMMA and inter-mixing of the PCL and PTL. Transient current measurements performed on metal–insulator–semiconductor devices containing an HPW/PMMA layer allowed the determination of both the concentration and mobility of the protons within this layer. Comparison of the extracted proton concentration (ca. 3.8 × 10 17 protons/cm 3) under full polarization conditions with the HPW concentration determined by UV spectroscopy indicates that only 2 protons per ∼1000 HPW molecules are mobile and contribute to the current. Finally, the material features of a generic PCL/PTL stacked structure affecting the operation of a molecular proton memory device are examined from a theoretical point of view. Results indicate that the write characteristics of this type of memory such as the magnitude of the memory window and the write speed depend on the thickness, the proton mobility and the proton concentration of the PCL, while the write voltage is mainly determined by the thickness of the PTL. In light of these analyses, it appears that memory windows as large as 2.8 V might be obtained for a 1 ms/3 V write operation regime even in the case of PCL and PTL thicknesses as high as 175 nm. These observations suggest that a PTL/PCL storage element may be well suited in future low-cost, low-power, and non-volatile single-organic transistor memory applications.

Electrically pumped ultraviolet random lasing from ZnO-based metal-insulator-semiconductor devices: Dependence on carrier transport

The electrically pumped ultraviolet (UV) random lasing and carrier transport of ZnO-based metal-insulator-semiconductor (MIS) structures on Si substrates have been systematically investigated. With the increase of positive bias voltage on the gates of the MIS devices, the current-voltage (I-V) characteristics manifest a normal curved I-V region where the current increases with the bias, followed by a negative differential resistance (NDR) region. Moreover, the UV electroluminescence from the devices in the normal region is transformed from spontaneous emission into increasingly intensive random lasing; while, that in the NDR region is transformed from random lasing into very weak spontaneous emission. The reason for the effect of NDR on the random lasing from the devices has been tentatively explored.

Photosensitive Metal–Insulator–Semiconductor Devices with Stepped Insulating Layer

A preparation procedure based on localized electrochemical oxidation unites multiple metal―insulator-semiconductor (MIS) junctions (also arrays) in a single device. The stepped enables a comparative study of several MIS junctions of different oxide thicknesses on one silicon wafer. We present a Si―SiO x ―Au four-step device with oxide thicknesses of 0, 1, 2.5, and 4 nm. The samples are characterized by internal photoemission using variable wavelengths (300―1100 nm). The nm junction shows an increased photosensitivity compared to the 0 nm junction (metal―semiconductor system). The internal photoemission drops by 2 orders of magnitude when increasing the oxide thickness from 1 to 4 nm.

Sputter-induced trap states at oxidized and grafted silicon surfaces: A comparative study

This paper analyzes the role of sputtering geometries on the conduction mechanism of metal–insulator–semiconductor devices where the insulating film is either SiO x or a grafted organic (sub)monolayer. The current–voltage characteristics were analyzed and correlated to the presence of traps in the band gap. The most influential defect was found to be related to interstitial Si (Si i ). We will show that its deactivation moves the Fermi level towards other defect/impurity levels depending on both the insulating layer and the deposition geometry. Si i density decrease is observed when samples are less exposed to sputtered particles and radiation flow, although major effects are also correlated to the degradation of the organic monolayer upon sputtering.

Memory effects in MIS structures based on silicon and polymethylmethacrylate with nanoparticle charge-storage elements

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on p-type silicon substrates and using polymethylmethacrylate (PMMA) as the dielectric. Gold nanoparticles, single-wall carbon nanotubes and C 60, deposited at room temperature, were used as charge-storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A relatively large memory window of about 2.2 V was achieved by scanning the applied voltage of an Al/PMMA/C 60/SiO 2/Si structure between 4 and −4 V. Gold nanoparticle-based memory devices produced the best charge retention behaviour compared to the other MIS structures investigated.

Enhanced electroluminescence of silicon-rich silicon nitride light-emitting devices by NH 3 plasma and annealing treatment

Silicon-rich silicon nitride (SRSN) films were deposited on p-type silicon substrates using a conventional plasma-enhanced chemical vapor deposition (PECVD) system. Before deposition, silicon substrate was pre-treated by NH 3 plasma in the PECVD system. And devices with metal–insulator–semiconductor (MIS) structure were fabricated using indium tin oxides (ITO) as anode and aluminum (Al) film as cathode. It was found that after 1100 °C annealing the electroluminescence (EL) intensity of NH 3 plasma pre-treated MIS devices was increased greatly comparing with that of without NH 3 plasma pre-treated devices. It is due to the passivation or reducing of interfacial states and nonradiative defects in SRSN films by the NH 3 plasma pre-treatment and high-temperature annealing that enhanced the EL intensity of the SRSN MIS devices.

Measurement of ultralow injection current to polymethyl-methacrylate film

Ultralow electron/hole injection currents from an electrode to a polymethyl-methacrylate (PMMA) film can be accurately decided by measuring the slow shift in the flatband voltage of a metal-insulator-semiconductor (MIS) device. It has been found that both the electron and hole injection currents are limited by the metal/PMMA interface and can be roughly described with a modified Richardson–Schottky equation. The space charge or dipole relaxation in PMMA films has been observed as well, which induces an instant change in flatband voltage of the MIS devices. These properties are critical issues for the stability of organic thin film transistors with PMMA gate insulator.

Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO 2/p-Si structure between 9 and −9 V.

Profiling of hydrogen in metal-insulator-semiconductor sensors using neutron reflectivity

Although interfacial hydrogen has long been accepted as the species responsible for H2 detection in metal-insulator-semiconductor (MIS) sensors, direct observation of this species has been elusive. In this work, the use of neutron reflectivity (NR) to quantify the hydrogen concentration in regions of an MIS device is reported. The presence of multiple states at both the metal-insulator interface and within the insulator that may contribute to the hydrogen response is suggested by the scattering length density profiles obtained from NR. This technique provides a great promise for direct study of the detection mechanisms for MIS sensors.

Analysis of Interface States in LaSixOy Metal–Insulator–Semiconductor Structures

Using a comprehensive model to simulate interface state effects on metal–insulator–semiconductor (MIS) device in capacitance–voltage (C–V) behavior, interface properties of LaSixOy gate dielectric MIS structures were analyzed. Under low temperature (400 °C) processing conditions amenable to low (0.6 nm) equivalent oxide thickness (EOT), LaSiO-based MIS capacitors on n- and p-type substrates have a high density localized interface state. The peak densities of this localized state for MIS devices on n- and p-type substrates are (2.0–2.5)×1013 and 2.5×1012 cm-2 eV-1, respectively, lying deep in the Si bandgap (within 0.1 eV of midgap). Positive fixed charge density is derived as in the range of 1013 cm-2 and is found to be distributed close to the interface region. In the case of the p-type MIS capacitor, positive fixed charge and positively charged interface states shift the C–V curve in the negative direction. Interface states in the n-type MOS capacitor capture electrons, compensating for the positive fixed charge and positively charged interface states. Thus less shift of the C–V curve is observed, compared to the p-type case. Interface state and fixed charge densities drastically reduce by raising post annealing temperature, to <1012 cm-2 eV-1 on n-type Si, but with concurrent EOT increase. Forming gas annealing (FGA) is effective for reducing the localized interface state density, but only when the temperature is 600 °C or higher. Results point to a need to minimize defect densities during or immediately after dielectric deposition. The high levels of positive defect states warrant further detailed investigation of the charge trapping characteristics of these dielectrics, as La-containing dielectrics are important for threshold voltage control for metal–oxide–semiconductor field effect transistor (MOSFET) devices.

Study of electrical properties of oxidized porous silicon for back surface passivation of silicon solar cells

Back surface passivation becomes a key issue for the silicon solar cells made with thin wafers. The high surface recombination due to the metal contacts can be lowered by reducing the back contact area and forming local back surface field (LBSF) in conjunction with the passivation with dielectric layer. About 3 × 10 - 7 m thick porous silicon (PS) layer with pore diameter mostly of 1 × 10 - 8 – 5 × 10 - 8 m was formed by chemical etching of silicon using the acidic solution containing hydrofluoric acid (HF), nitric acid (HNO 3) and De-ionized water in the volume ratio 1:3:5 at 298 K for which etching time was kept constant for 360 s. Electrical properties of oxidized PS was studied through the current–voltage ( I – V ) and capacitance–voltage ( C – V ) characteristics of the metal–insulator–semiconductor (MIS) device in which the oxidized PS was used as an insulating layer and the results were further analyzed. The C – V curves of all the studies MIS devices showed the negative flatband voltage varying from - 2 to - 5 V , confirming that the oxidized layer of PS has fixed positive charge.

Carbon nano dots scale by focused ion beam system for MIS diode nano devices

Metal–insulator–semiconductor (MIS) structures with a nanocrystal carbon (nc-C) embedded in SiO 2 thin films were fabricated using a focused ion beam (FIB) system with a precursor of low-energy Ga + ion and carbon source. The crystallinity of nc-C was investigated by Raman spectroscopy and atomic force microscopy (AFM). Raman spectra indicate the evidence of crystallization of nc-C after annealed at 600 °C by the sharp peak at 1565 cm −1 in graphite (sp 2), while no peak of diamond (sp 3) could be seen at 1333 cm −1. The AFM images showed the nc-C dots controlled with diameter of 100 nm, 200 nm and 300 nm, respectively. The above results revealed that the nc-C dots had sufficiently stuck onto SiO 2 films. The hysterisis loop in the capacitance–voltage characteristics appeared in the MIS device with SiO 2/nc-C/SiO 2 structure in which voltage shift is 0.32 V for radical oxidation and 0.14 V for dry oxidation, respectively.

Interface states in polyfluorene-based metal–insulator–semiconductor devices

Hybrid metal–insulator–semiconductor structures based on ethyl-hexyl substituted polyfluorene (PF2/6) as the active polymer semiconductor were fabricated on a highly doped p-Si substrate with Al 2 O 3 as the insulating oxide layer. We present detailed frequency-dependent capacitance–voltage ( C – V ) and conductance–voltage characteristics of the semiconductor/insulator interface. PF2/6 undergoes a transition to an ordered crystalline phase upon thermal cycling from its nematic-liquid crystalline phase, confirmed by our atomic force microscope images. Thermal cycling of the PF2/6 films significantly improves the quality of the (PF2/6)/Al 2 O 3 interface, which is identified as a reduced hysteresis in the C – V curve and a decreased interface state density ( D it ) from ∼3.9 × 10 12 eV −1 cm −2 to ∼3.3 × 10 11 eV −1 cm −2 at the flat-band voltage. Interface states give rise to energy levels that are confined to the polymer/insulator interface. A conductance loss peak, observed due to the capture and emission of carriers by the interface states, fits very well with a single time constant model from which the D it values are inferred.

Metal-insulator-semiconductor structure on low-temperature grown GaAs

The metal-insulator-semiconductor (MIS) capacitors on low-temperature grown (LTG) GaAs were made using the jet-vapor-deposition (JVD) silicon nitride as the gate dielectrics. The unpinned JVD-SiN/LTG-GaAs interface was shown by the capacitance-voltage characterization. The observed Fermi level “pinning” in the unannealed samples was caused by the bulk point defects in LTG GaAs. Annealing reduced the bulk defect density in LTG GaAs and revealed the intrinsically unpinned Fermi level at the interface. The result is consistent with the expected unpinning of LTG GaAs surface, and JVD SiN appears to play a critical role to enable this unpinned interface. JVD SiN showed low leakage current (∼10nA∕cm2 at 2MV∕cm) and high breakdown electric field (∼9.8MV∕cm), promising for MIS device applications.

Electron trapping and inversion layer formation in photoexcited metal-insulator-poly(3-hexylthiophene) capacitors

Photocapacitance measurements are reported on metal-insulator-semiconductor (MIS) capacitors employing polyimide (PI) or polysilsesquioxane (PSQ) as the gate insulator and poly(3-hexylthiophene) as the active semiconductor. By stressing devices into depletion while simultaneously irradiating with light of energy exceeding the semiconductor band gap, photogenerated electrons become trapped at the insulator/semiconductor interface or possibly in bulk insulator states. Additionally for the PSQ device, evidence is provided for the formation of a photogenerated inversion layer at the interface. The time dependence of electron detrapping in the PI case is similar to that observed for accumulation stress instability in organic MIS devices.

High-Temperature Stability of Lanthanum Silicate Gate Dielectric MIS Devices with Ta and TaN Electrodes

The high-temperature stability of lanthanum silicate gate dielectric metal-insulator-semiconductor (MIS) devices with either Ta or electrodes has been studied. After a , rapid thermal annealing (RTA) treatment, devices with Ta gate metal undergo an equivalent oxide thickness (EOT) increase from 0.62 to or higher, while devices with as the gate electrode experience an EOT increase from 0.62 to only . An EOT less than is achieved after a RTA, with a corresponding gate leakage of . Medium-energy ion scattering and X-ray diffraction (XRD) analysis reveal that the Ta gate metal undergoes a phase change due to reaction with above , while for no change in the XRD spectrum is detected. Interface state defect densities and leakage currents are reduced after the high-temperature processing. Results reveal the importance of the entire gate stack design and processing in obtaining good device properties.

Deep traps influence in polycrystalline diamond electrical transport charge

The influence of interfacial states of energy arising from defects in the metal-Microwave Plasma Assisted Chemical Vapor Deposition (MPCVD) diamond Schottky interface has been investigated by electrical DC measurements, in time and temperature. A significant temperature-dependent applied-bias offset for zero current conditions (near 0.3V at room temperature) is noticed. At room temperature the decay constant is about 0.1s. The current–voltage behavior is strongly dependent on the environment conditions, air or vacuum. This dependence ceases after the application of a high forward electrical field. The electrical conduction shows activation energies near 0.1eV with differences with the applied voltage time. Under near UV–visible photoexcitation, the photodiode shows a high current gain (up to three orders of magnitude) and a corresponding relatively high short circuit current. A model involving states of energy inside an interfacial layer acting as traps for the majority carriers is discussed. A potential application in metal–insulator–semiconductor devices is focused.

I–V Characteristics of tris(2,4-pentanedionato)manganese(III) thin films

Amorphous thin films of tris(acetylacetonate)manganese(III) were deposited on Si(P) substrates by thermal sublimation in vacuum. The deposited films were probed with X-ray fluorescence. Their electrical properties were studied as insulators for Al/Mn(acac)3/Si(P) metal–insulator–semiconductor devices. Those devices were characterized by the measurement of the gate-voltage dependence of their capacitance, from which the relative permittivity (RP) and density of the charges in the insulator were determined. It was found that values of the RP of tris(acetylacetonate)manganese(III) films grown on Si(P) wafers were in the range of 30–40, which can be find applications in gate related technological uses. The dc-electrical conduction in the complex film was studied at room temperature and in temperature range of (293–325K). It was found that the data of the as-deposited films follow the trap-charge-limited space-charge-limited conductivity (TCL-SCLC) mechanism, while the data of the annealed sample in vacuum of about 10−3Pa at about 100°C for 10min obey the Richardson–Schottky (RS) mechanism. The parameters of both mechanisms were determined. It was concluded that the density of charged defects in the insulating film is critically determined the mechanism of the current-transfer.