Analysis of Interface States in LaSixOy Metal–Insulator–Semiconductor Structures

Abstract

Using a comprehensive model to simulate interface state effects on metal–insulator–semiconductor (MIS) device in capacitance–voltage (C–V) behavior, interface properties of LaSixOy gate dielectric MIS structures were analyzed. Under low temperature (400 °C) processing conditions amenable to low (0.6 nm) equivalent oxide thickness (EOT), LaSiO-based MIS capacitors on n- and p-type substrates have a high density localized interface state. The peak densities of this localized state for MIS devices on n- and p-type substrates are (2.0–2.5)×1013 and 2.5×1012 cm-2 eV-1, respectively, lying deep in the Si bandgap (within 0.1 eV of midgap). Positive fixed charge density is derived as in the range of 1013 cm-2 and is found to be distributed close to the interface region. In the case of the p-type MIS capacitor, positive fixed charge and positively charged interface states shift the C–V curve in the negative direction. Interface states in the n-type MOS capacitor capture electrons, compensating for the positive fixed charge and positively charged interface states. Thus less shift of the C–V curve is observed, compared to the p-type case. Interface state and fixed charge densities drastically reduce by raising post annealing temperature, to <1012 cm-2 eV-1 on n-type Si, but with concurrent EOT increase. Forming gas annealing (FGA) is effective for reducing the localized interface state density, but only when the temperature is 600 °C or higher. Results point to a need to minimize defect densities during or immediately after dielectric deposition. The high levels of positive defect states warrant further detailed investigation of the charge trapping characteristics of these dielectrics, as La-containing dielectrics are important for threshold voltage control for metal–oxide–semiconductor field effect transistor (MOSFET) devices.