Metal-insulator-semiconductor Devices Research Articles

Analysis on the capacitance-voltage characteristics of metal-insulator-semiconductor capacitors based on thermally evaporated WOx on n- and p- type crystalline silicon

Tungsten oxide (WOx) thin films were deposited on n- and p-type crystalline silicon (c-Si) wafers by thermal evaporation technique at room temperature. The electrical characterization of Ag/WOx/n-Si and Ag/WOx/p-Si metal–insulator-semiconductor (MIS) capacitors were examined by the capacitance- and conductance-voltage measurements as a function of applied frequency in the 10 kHz 10 MHz range. The admittance properties of both MIS devices have been evaluated by analyzing the interfacial nature and bulk c-Si in accumulation, depletion, and inversion regimes. The capacitance responses of interface traps, bulk c-Si, depletion, and shallow states at the WOx/c-Si interface indicated the appearance of the capacitance peaks in depletion and inversion regimes for Ag/WOx/n-Si and Ag/WOx/p-Si devices. From C-V characterization, various parameters such as the depletion layer width, depletion capacitance, flat-band voltage, total charge density, and net ionized state density were calculated as a function of applied frequency. For Ag/WOx/n-Si device, the total charge density and barrier height values of 7.642 × 10−9 C and 1.119 eV at 1 MHz, respectively, were obtained. The same parameters were calculated to be 5.887 × 10−8 C and 1.107 eV for Ag/WOx/p-Si. The results demonstrated that interfacial nature of WOx film significantly governs the electronic characteristics of the c-Si based MIS devices.

Two-dimensional localization in GeSn

Localization behaviour is a characteristic feature of the p-type GeSn quantum well (QW) system in a metal–insulator–semiconductor device. The transition to strongly localized behaviour is abrupt with thermally activated conductivity and a high temperature intercept of 0.12 × e 2 ħ −1 at a hole carrier density 1.55 × 1011 cm−2. The activation energy for the conductivity in the localized state is 0.40 ± 0.05 meV compared to an activation energy of ∼0.1 meV for conductivity activation to a mobility edge at carrier densities >1.55 × 1011 cm−2. Insulating behaviour can occur from a system that behaves as though it is in a minimum metallic state, albeit at high temperature, or from a conductivity greater than a minimum metallic state behaviour showing that local disorder conditions with local differences in the density of states are important for the onset of localization. In the presence of a high magnetic field, thermally activated conductivity is present down to Landau level filling factor < but without a magnetic-field-dependent carrier density or a variable range hopping (VRH) transport behaviour developing even with conductivity ≪e 2 h −1. In the localized transport regime in p-type doped Ge0.92Sn0.08 QWs the VRH mechanism is suppressed at temperatures >100 mK and this makes this two-dimensional system ideal for future many body localization studies in disordered hole gases that can be thermally isolated from a temperature reservoir.

The electrical characterization of metal–insulator–semiconductor device with β-naphthol orange interface

The electrical characterization of metal–insulator–semiconductor device with β-naphthol orange interface

Low trap density of oxygen-rich HfO2/GaN interface for GaN MIS-HEMT applications

The high-k nature of HfO2 makes it a competitive gate oxide for various GaN-based power devices, but the high trap densities at the HfO2/GaN interface have hindered the application. This work was specifically carried out to explore the interface between GaN and ozone-based atomic-layer-deposited HfO2 gate oxide. Furthermore, the GaN surface is preoxidized before gate oxide deposition to prepare an oxygen-rich HfO2/GaN interface. On the preoxidized GaN surface, a sharper HfO2/GaN interface and amorphous HfO2 bulk form during the subsequent deposition, translating to improved electric performance in metal–insulator–semiconductor (MIS) devices. The ozone-based HfO2 shows a high breakdown electric field (∼7 MV/cm) and a high dielectric constant (∼28). Furthermore, the MIS high electron mobility transistors' negligible VTH hysteresis and parallel conductance measurements reflect the ultralow trap densities of the HfO2/GaN interface (&amp;lt;1012 cm−2 eV−1). Therefore, the proposed HfO2 gate oxide scheme offers a promising solution for developing GaN MIS devices.

Modified Ramped Current Stress Technique for Monitoring Thin Dielectrics Reliability and Charge Degradation

Herein, a novel technique to monitor the quality and reliability of thin nano‐scale dielectric films is suggested. The method is based on the modification of the current stress technique (J‐Ramp) described in the corresponding JEDEC standard. The proposed technique, in addition to the J‐ramp tests, allows monitoring a change of charge state of the gate dielectric during all the tests. To implement this, in the suggested method before each transition to a higher current level, the current level is switched to the injection mode by a measurement current level and the change of voltage across the metal–insulator–semiconductor (MIS) structure is measured. A density of the measurement current level is chosen based on the condition that under this current level, a considerable charge degradation of the dielectric should not be observed, and the switches to the measurement current level should not considerably influence the studied sample. In addition to the monitoring of the charge injected until the dielectric breakdown, the proposed method allows to monitor the value of the injected charge at which the unacceptable degradation of MIS device characteristics takes place and, accordingly, to estimate the reliability of the dielectric film based on statistical measurements of these values.

Annealing temperature influenced physical properties of Al2TiO5 thin films for MIS devices

Aluminium titanate (Al2TiO5) thin films were deposited at room temperature by DC reactive magnetron sputtering. To make appropriate films for potential gate dielectric applications, we investigated the influence of annealing temperature on the structural, chemical and dielectric properties of Al2TiO5 thin films. From XPS studies, in as-deposited films, it has been observed that the presence of Al3+ and Ti4+oxidation states which correspond to Al2O3 and TiO2 respectively. After annealing at 400 °C in oxygen ambient, the binding energies of Al 2p, Ti 2p and O 1s were shifted by ~ 1 eV towards lower binding energy. This indicates the formation of an intermediate compound of Al2O3 and TiO2. The extracted Al, Ti and O ratio was 2:1:5 and it confirms the formation of Al2TiO5. XRD studies indicate that the as-deposited films were amorphous in nature. After annealing at 400 °C, diffraction peak at 2θ = 50.6° along (200) plane corresponds to aluminum titanate (Al2TiO5) has been observed. Metal-Insulator-Semiconductor (MIS) capacitors were fabricated and characterized to estimate the dielectric properties of the deposited films. The as-deposited films show low dielectric constant (κ = 8.1) and high leakage current density (J = 2.4x10-2 A/cm2 at -1V) values. After annealing at 400 °C the films show improved dielectric constant (κ = 9.4) and leakage current density (J = 4.6x10-9 A/cm2 at -1V) values. The enhancement in the device properties can be attributed to the improved oxide and interface quality after annealing. Equivalent oxide thickness (EOT) of less than 1nm is required to use Al2TiO5 as an alternate gate dielectric to SiO2 in CMOS industry. To achieve this scaling of the dielectric thickness (<5 nm) is needed, which is under investigation. Copyright © 2017 VBRI Press.

Passivation of miniature microwave coplanar waveguides using a thin film fluoropolymer electret

The insertion losses of miniature gold/silicon-on-insulator (SOI) coplanar waveguides (CPW) are rendered low, stable, and light insensitive when covered with a thin film (95 nm) fluoropolymer deposited by a trifluoromethane (CHF3) plasma. Microwave characterization (0–50 GHz) of the CPWs indicates that the fluoropolymer stabilizes a hydrogen-passivated silicon surface between the CPW tracks. The hydrophobic nature of the fluoropolymer acts as a humidity barrier, meaning that the underlying intertrack silicon surfaces do not re-oxidize over time—something that is known to increase losses. In addition, the fluoropolymer thin film also renders the CPW insertion losses insensitive to illumination with white light (2400 lx)—something potentially advantageous when using optical microscopy observations during microwave measurements. Capacitance–voltage (CV) measurements of gold/fluoropolymer/silicon metal–insulator-semiconductor (MIS) capacitors indicate that the fluoropolymer is an electret—storing positive charge. The experimental results suggest that the stored positive charge in the fluoropolymer electret and charge trapping influence surface-associated losses in CPW—MIS device modelling supports this. Finally, and on a practical note, the thin fluoropolymer film is easily pierced by commercial microwave probes and does not adhere to them—facilitating the repeatable and reproducible characterization of microwave electronic circuitry passivated by thin fluoropolymer.

Enhanced Photo Sensing and Lowered Power Consumption in Concentric MIS Devices by Monitoring Outer Ring Open-Circuit Voltage With Biased Inner Gate

Concentric metal-insulator-semiconductor (MIS) structure is used as a photo sensor. Generally, the outer ring acts as gate and the inner circle acts as sensor. In this article, by changing the sensing method from measuring light current to measuring open-circuit voltage of floating sensor, power consumption is considerably lowered. Moreover, by exchanging conventional role of inner device and outer ring, photo-sensitivity under extremely weak light is also highly enhanced, and it results from asymmetric coupling effect of inner circle and outer ring. Furthermore, our device shows great performance as well when using light current as alternative sensing signal in the conventional way.

DETERMINATION OF MAIN ELECTRICAL PARAMETERS OF Au–4H-n-SiC (MS) AND Au–Al2O3–4H-n-SiC (MIS) DEVICES

In this study, Au–4H-[Formula: see text]-SiC metal–semiconductor (MS) and Au–Al2O3–4H-[Formula: see text]-SiC metal–insulator–semiconductor (MIS) devices were fabricated to examine the effects on the performance of electronic devices of interfacial insulating materials. In order to determine the dielectric properties, capacitance/conductance–voltage ([Formula: see text]–[Formula: see text] measurements were realized in a wide range of voltages ([Formula: see text]3.0 V)–(11.0 V). Current–voltage ([Formula: see text]–[Formula: see text] measurements to obtain the electric properties were realized at [Formula: see text][Formula: see text]V. Moreover, both the energy distributions of surface states ([Formula: see text] and series resistance ([Formula: see text] were obtained from the [Formula: see text]–[Formula: see text] data. Obtained results provided that series resistance originating from interfacial layer (Al2O[Formula: see text] was more effective on the [Formula: see text]–[Formula: see text] and [Formula: see text]–[Formula: see text] characteristics which must be taken into account in the calculation of main electrical parameters. The rectification ratio (RR) and shunt resistance ([Formula: see text] of the MIS device were almost 103 times greater than those of the MS structure. Using Al2O3 between Au and 4H-[Formula: see text]-SiC also led to an increase in the value of barrier height (BH) and a decrease in the value of ideality factor ([Formula: see text]. These results confirmed that Al2O3 layer leads to an increase in the performance of MS device with respect to low values of [Formula: see text], reverse saturation current ([Formula: see text] and [Formula: see text] and high values of RR, [Formula: see text] and BH.

Ultra-dry air plasma treatment for enhancing the dielectric properties of Al2O3-GPTMS-PMMA hybrid dielectric gate layers in a-IGZO TFT applications

We assessed the effects of ultra dry-air plasma surface treatments on the properties of Al2O3-GPTMS-PMMA hybrid dielectric layers for applications to high-performance amorphous Indium Gallium Zinc Oxide (a-IGZO) thin film transistors (TFTs). The hybrid layers were deposited by an easy dip coating sol-gel process at low temperature and then treated with dry-air plasma at 1, 2 and 3 consecutive cycles. Their properties were analyzed as a function of the number of plasma cycles and contrasted with those of the untreated ones. The dielectric characteristics of the hybrid layers were determined from I–V and C–f measurements performed on metal–insulator–metal and metal–insulator–semiconductor devices. The results show that the plasma treatments increase the surface energy and wettability of the hybrid films. There is also a reduction of the OH groups and oxygen vacancies in the hybrid network improving the dielectric properties. The incorporation of nitrogen into the hybrid films surface is also observed. The plasma-treated hybrid dielectric layers were applied as dielectric gate in the fabrication of a-IGZO TFTs. The best electrical performance of the fabricated TFTs was achieved with the 3 cycles plasma-treated hybrid dielectric gate, showing high mobility, 29.3 cm2 V−1 s−1, low threshold voltage, 2.9 V, high I ON/OFF current ratio, 106, and low subthreshold swing of 0.42 V dec−1.

Admittance of barrier nanostructures based on MBE HgCdTe

Mid- and long-wave infrared nBn structures based on HgCdTe grown by molecular beam epitaxy (MBE) on GaAs (013) substrates were fabricated. For mid-wave nBn structures, the composition in the absorbing layer was 0.29, and for long-wave nBn structures, this composition was 0.21. The composition in the MBE HgCdTe barrier layers ranged from 0.61 to 0.67. Based on the fabricated HgCdTe nBn structures, test metal–insulator–semiconductor (MIS) devices were created by applying a dielectric Al2O3 film with the thickness of about 90 nm. The admittance of test MIS devices was investigated over a wide range of frequencies and temperatures. An equivalent circuit of MIS device based on MBE HgCdTe nBn structure is proposed, which includes the dielectric capacitance, the capacitance and resistance of the barrier layer, and the series resistance of the absorbing layer bulk. It is shown that the values of the equivalent circuit elements are easy to determine from the experimental frequency dependences of admittance in accumulation mode. Comparison of element values for MIS devices based on mid-wave and long-wave nBn structures is carried out.

Hafnium-zirconium oxide interface models with a semiconductor and metal for ferroelectric devices.

Density functional theory (DFT) is employed to investigate ferroelectric (FE) hafnium–zirconium oxide stack models for both metal–insulator–metal (MIM) and metal–insulator–semiconductor (MIS) structures. The role of dielectric (DE) interlayers at the ferroelectric interfaces with metals and semiconductors and the effects of thickness scaling of FE and DE layers were investigated using atomic stack models. A high internal field is induced in the FE and DE layers by the FE polarization field which can promote defect generation leading to limited endurance. It is also shown that device operation will be adversely affected by too thick DE interlayers due to high operating voltage. These DFT models elucidate the underlying mechanisms of the lower endurance in experimental MIS devices compared to MIM devices and provide insights into the fundamental mechanisms at the interfaces.

Low-temperature Hf-silicate prepared with various thermal budgets

In this study, the influence of thermal budget on preparing hafnium silicate (HfSiO) and metal–insulator–semiconductor (MIS) structures with tetragonal hafnium oxide (HfO2) films was investigated. Amorphous silicon (a-Si) was used as a sacrificial layer for HfSiO formation. Rapid thermal annealing (RTA) could efficiently drive the oxidation of a-Si with HfO2. The RTA-produced HfSiO film thicker than that produced through furnace annealing could suppress gate leakage in MIS devices, and aid in maintaining a high dielectric constant of the gate insulator. The combination of sacrificial a-Si film use and RTA application resulted in a HfSiO/HfO2 structure (named as hybrid HfO2), which demonstrated a high dielectric constant and strength (29.5 and 21.2 MV cm−1, respectively). MIS devices integrated with this hybrid HfO2 achieved a hysteresis value of only 0.11 V on a flat-band voltage measured at a 50 mV s−1 sweep rate with an applied voltage between −5 and 5 V.

Reliability Characteristics of Diamond-Like Carbon as Gate Insulator for Metal–Insulator–Semiconductor Application

This study presents the reliability of diamond-like carbon (DLC) ultrathin films fabricated by DC magnetron sputtering as the gate dielectric layer in metal–insulator–semiconductor (MIS) devices. Stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) measurements were performed to determine the reliability of the devices. The MIS device with DLC film deposited at 1100-V bias exhibited little variation of SILC under different constant voltage stress times and had a long TDDB lifetime. The results indicate excellent reliability of DLC films used as gate dielectrics. Moreover, several soft breakdown events occurred during TDDB measuring. An extended percolation model was adopted for explanation of the current versus time characteristics.

Fabrication and characterization of metal insulator semiconductor Ag/PVA/GO/PVA/n-Si/Ag device

In this work, Metal Insulator Semiconductor (MIS) device is fabricated by depositing Graphene Oxide (GO) layer between the top and bottom Polyvinyl Alcohol (PVA) layers to act as an insulating layer. Topographical study of Ag/PVA/GO/PVA/n-Si/Ag device is done by Field Emission-Scanning Electron Microscopy (FE-SEM) technique. The image clearly showed the multilayered sandwiched structure having GO embedded between PVA layers. The comparative study of the effect of interface trap states, series resistance (Rs) and an insulating layer on the different layers of device performance is done using capacitance-conductance characteristics. The presence of peaks in capacitance-conductance curves revealed the presence of interface trap states in the fabricated device. The C–V measurements were taken in the frequency range of 5 kHz to 1 MHz. The interfacial state density (Nss) is found to be of the order of 1011 cm−2 eV−1 which is calculated using Hill-Coleman's method. The increase in leakage current through residual native oxide is verified by calculating the series resistance. The deviation from the ideal behavior of capacitance and conductance characteristics is observed which is attributed to Nss and Rs. The device fabricated unfolded the existence of the capacitance roll-off phenomenon.

Highly accurate tuning of current–voltage characteristic shift in a photo-sensitive three terminal metal–insulator–semiconductor device

We present a planar three terminal device fabricated on a silicon-on-insulator substrate. The device is based on a two-layer dielectric stack comprising SiO2 tunneling and HfO2 layers. A so-called gate electrode is placed between two other contacts, of the source and drain, all deposited on the insulator stack. In the dark as well as under illumination, the current–voltage characteristic can be shifted in an ideal linear manner with changes in a positive gate voltage with the shift being somewhat larger under illumination. The reason for the change of shift is the ability of high-density oxygen vacancies, arranged in the filament regions within an HfO2 sublayer that was voltage stress. Namely, holes or electrons are trapped in the HfO2 sublayer, respectively, from the inverted or accumulated Si layer. This process is controlled by the gate and drain bias levels. Moreover, under illumination and at negative gate and drain voltages, the device exhibits negative differential resistance caused by capture of photo-generated minority carriers induced in the depletion region of the Si after they tunnel through the SiO2 layer by negative oxygen vacancies that migrate to the SiO2/HfO2 interface through the filament regions. Finally, the low level of saturation current in the dark and the ability to precisely control its value by illumination intensity, together with a large sensitivity of 80–85 A/W and 25 A/W, at 490 nm and 365 nm, respectively, allow additional applications that cannot be achieved with conventional MIS devices.

Admittance of metal–insulator–semiconductor devices based on HgCdTe nBn structures

Metal-insulator-semiconductor (MIS) structures were fabricated by depositing an Al2O3 dielectric on top of the contact layer of a mid-wave infrared nBn detector based on n-Hg1-xCdxTe grown by molecular beam epitaxy on GaAs (013) substrates. It is shown that when creating a backward electrode on the absorbing layer, the form of the capacitance–voltage characteristics depends not only on the properties of the contact layer, but also on the properties of the barrier and absorbing layers. An equivalent circuit of MIS structure based on nBn detector with mesa configuration is proposed. It is shown that measurements of the admittance of MIS structures with mesa configuration allow one to study the properties of the barrier layer in the nBn structure. The influence of infrared radiation on the temperature dependence of the barrier layer resistance is studied.

Effect of surface treatment on electrical properties of GaN metal–insulator–semiconductor devices with Al2O3 gate dielectric

This research proposes an economical and effective method of 1-octadecanethiol (ODT) treatment on GaN surfaces prior to Al2O3 gate dielectric deposition. GaN-based metal–insulator–semiconductor (MIS) devices treated by HCl, O2 plasma and ODT are demonstrated. ODT treatment was found to be capable of suppressing native oxide and also of passivating the GaN surface effectively; hence the interface quality of the device considerably improved. The interface trap density of Al2O3/GaN was calculated to be around 3.0 × 1012 cm−2 eV−1 for devices with ODT treatment, which is a relatively low value for GaN-based MIS devices with Al2O3 as the gate dielectric. Moreover, there was an improvement in the gate control characteristics of MIS-HEMTs fabricated with ODT treatment.

Interface charge engineering in AlTiO/AlGaN/GaN metal–insulator–semiconductor devices

Toward interface charge engineering in AlTiO/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, we systematically investigated insulator-semiconductor interface fixed charges depending on the composition of the AlTiO gate insulator obtained by atomic layer deposition. By evaluating the positive interface fixed charge density from the insulator-thickness dependence of the threshold voltages of the MIS devices, we found a trend that the interface fixed charge density decreases with the decrease in the Al composition ratio, i.e., increase in the Ti composition ratio, which leads to shallow threshold voltages. This trend can be attributed to the large bonding energy of O-Ti in comparison with that of O-Al and to consequent possible suppression of interface oxygen donors. For an AlTiO gate insulator with an intermediate composition, the MIS field-effect transistors exhibit favorable device characteristics with high linearity of transconductance. These results indicate a possibility of interface charge engineering using AlTiO, in addition to energy gap engineering and dielectric constant engineering.

Charge Effects in the Dielectric Films of MIS Structures under the Concurrent Influence of Radiation and High-Field Electron Injection

Based on the obtained experimental data, a model is developed for the processes of a variation in the charge state of MIS (metal–insulator–semiconductor) structures under the concurrent influence of high-field tunneling electron injection and radiation. The model takes into account the interaction between injected electrons and charges appearing in the dielectric film due to radiation and high-field ionization. It is shown that some holes may be annihilated during the interaction between injected electrons and holes trapped in a SiO2 film, thus leading to the formation of surface states at the interface with silicon. The effect of the electric-field intensity and injection current density on the generation and annihilation of positive charge and the formation of surface states under radiation is studied. The effect of charge processes occurring in the insulator film of a MIS structure under the concurrent action of radiation and high-field electron injection on a change in the threshold voltage of MIS devices and radiation sensors based on them is considered.