Metal Grain Granularity Research Articles

An accurate machine learning model to study the impact of realistic metal grain granularity on Nanosheet FETs

In this work, we present a machine learning neural network model to predict the impact of realistic metal grain granularity (MGG) variability on the threshold voltage VTh and on the ID−VG characteristics of a silicon-based 12 nm gate length nanosheet FET. This model is based on the multi-layer perceptron (MLP) machine learning architecture. As realistic MGG maps consist of the distribution of grains on the gate with different work-function values, it is relevant to apply algorithms such as the principal component analysis to reduce these features to the most representative ones. Once the realistic MGG features are correctly reduced without losing information, we train two different neural networks with the neurons in the output layer as the only difference, to predict the VTh and the ID−VG characteristics, respectively. The comparison between TCAD results and the model, shows excellent agreement for the mean and standard deviation of VTh distributions for different average grain sizes values (from 3 nm to 10 nm) demonstrating the accuracy of the machine learning model. Also, we study the amount of data needed to accurately train the MLPs, leading to results that allow us to drastically reduce the computational time required to perform variability studies for state-of-art nano FET devices.

A comprehensive Pelgrom-based on-current variability model for FinFET, NWFET and NSFET

We present a novel Pelgrom-based predictive (PBP) model to estimate the impact of variability on the on-current of different state-of-the-art semiconductor devices. In this work, we focus on two of the most problematic sources of variability, the metal grain granularity (MGG) and the line edge roughness (LER). This model allows us to make an accurate prediction of the on-current standard deviation σIon, being the relative error of the predicted data lower than 8% in 92% of the studied cases. The PBP model entails an immense reduction in the computational cost since once it is calibrated for an architecture, the prediction of the impact of a variability on devices with any given dimension can be made without any further simulations. This model could be useful for predicting the effect of variability on future technology nodes.

Simulations of Statistical Variability in n-Type FinFET, Nanowire, and Nanosheet FETs

Four sources of variability, metal grain granularity (MGG), line-edge roughness (LER), gate-edge roughness (GER), and random discrete dopants (RDD), affecting the performance of state-of-the-art FinFET, nanosheet (NS), and nanowire (NW) FETs, are analysed via our in-house 3D finite-element drift-diffusion/Monte Carlo simulator that includes 2D Schrödinger equation quantum corrections. The MGG and LER are the sources of variability that influence device performance of the three multi-gate architectures the most. The FinFET and the NS FET are similarly affected by the MGG variations with threshold voltage and on-current standard deviations significantly lower (at least 20 %) than those of the NW FET. The LER variability has a negligible influence in the NS FET performance with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma ~{V}_{T}$ </tex-math></inline-formula> values around 12 and 42 times lower than those of the FinFET and the NW FET. The three architectures are equally affected by the RDD ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T}$ </tex-math></inline-formula> = 8 mV) and minimally influenced by the GER ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma {V}_{T} \approx 4$ </tex-math></inline-formula> mV). The variability of NS FETs makes them strong candidates to replace FinFETs.

Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the viable solutions toward scaling down below sub-7nm technology nodes. In this work, we compare electrical performance, including variability studies of several horizontal nanosheet transistors toward transistor structure optimization. We explore the impacts of nanosheet width and thickness on the electrical performance and outline important design guidelines necessary for vertically stacked nanosheet FETs. An increase in the complexity of the stacked nanosheet structures can lead to significant device variability. Using numerical simulation, we study the characteristics fluctuations induced by the random discrete dopants (RDD) and metal grain granularity (MGG) in nanosheet gate-all-around (GAA) transistors. We use 3-D quantum-mechanically corrected transport models in the simulation. It is observed that the σVTH due to MGG variability is 12% higher than RDD variability while the RDD variability strongly influences the ION. The statistical simulation results predict that the presence of combined variability due to RDD and MGG strongly influences the threshold voltage variation (σVTH) in nanoscale devices. This approach may be applied to the different types of variability, the geometry of the device, including the vertical and lateral dimensions of the transistor, and biasing conditions.

Does the Threshold Voltage Extraction Method Affect Device Variability?

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using data from the IV curve. In this work, we use numerical simulations to evaluate the effect of the threshold voltage ( $\mathrm {V_{TH}}$ ) extraction method on the variability estimation for a gate-all-around nanowire FET. For that, we analyse the impact of four sources of variability: gate edge roughness (GER), line edge roughness (LER), metal grain granularity (MGG) and random discrete dopants (RDD). We have considered five different extraction methods: the second derivative (SD), constant current (CC), linear extrapolation (LE), third derivative (TD) and transconductance-to-current-ratio (TCR). For the ideal non-deformed device at high drain bias, the effect of the extraction technique can lead to a 137 mV difference in $\mathrm {V_{TH}}$ and an 89 mV/V difference in the drain-induced-barrier-lowering (DIBL), and when considering GER and LER variability, the influence of the extraction method leads to differences in the standard deviation values of the $\mathrm {V_{TH}}$ distribution ( $\sigma \mathrm {V_{TH}}$ ) of up to 2.3 and 3.7 mV respectively, values comparable to intrinsic parameter variations. Therefore, the $\mathrm {V_{TH}}$ extraction technique presents itself as an additional parameter that should be included in performance comparisons as it can heavily impact the results.

Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors

Using physics-based predictive technology CAD simulations, we show the improvements possible in device performance via strain engineering in vertically-stacked horizontal gate-all-around nanosheet Field-Effect transistors (NSFETs), which may outperform conventional FinFETs beyond 7 nm technology node. Effects of mechanical strain on NSFET variability is reported for the first time. We present a novel simulation approach for the analyses of random dopant fluctuation (RDF) and metal grain granularity (MGG) dependent variability in nanosheet transistors. The study encompasses topography simulation, which realistically reproduces a reported experimental nanosheet transistor. Device simulations are based on sub-band Boltzmann transport with 2D Schrödinger equation in the nanosheet cross-section and 1D Boltzmann transport along the nanosheet channel. The effects of mechanical stress and geometry dependence of the electrical characteristics are also reported. Critical design issues are outlined.

Vertically-stacked silicon nanosheet field effect transistors at 3 nm technology nodes - simulation at nanoscale

Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3 nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. In this work, we use 3D predictive simulations to study the performance potential of SNS-FETs at 3 nm technology node. With the end of happy scaling era, change of device architecture has raised integration complexity along with severe short channel effects, mobility degradation, variability and quantum tunnelling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7 nm. Towards low power and high speed (more-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the possibility of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass FinFETs. Variability due to metal grain granularity (MGG) is critical at 3 nm technology nodes, as such, the device threshold voltage variation due to MGG is examined for single nanosheet NS-FET. Finally, we calculate the mean and standard deviation of these parameters to quantify the variability.

Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.

Fin Shape Dependence of Electrostatics and Variability in FinFETs

The performance of advanced nanoscale devices is limited by different process variability issues, including patterning proximity effects. Most manufactured fin-shaped field-effect transistors (FinFETs) have some imperfections in the fin shape due to imperfections in lithography and deformation due to other high-temperature process steps. In this work, full three-dimensional (3D) device simulations are performed to study the effects of such variability in the fin shape on the electrostatics of trigate FinFETs. Variability due to random discrete dopants (RDDs) and metal grain granularity (MGG) is considered separately and in combination. The device threshold voltage variation due to RDDs and MGG is critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability. It is shown that there is a strong correlation between the drain-induced barrier lowering (DIBL) and random discrete dopant position in the channel.

Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET

The effect of gate edge roughness (GER) in the sub-threshold region is studied for two state-of-the-art architectures: a 10.7-nm Si FinFET and a 10-nm Si gate-all-around (GAA) nanowire (NW) FET using an in-house 3D quantum-corrected drift-diffusion simulation tool. The GER is applied to the device gate using the characteristic values of root-mean-square amplitude and correlation length (CL). The GER-induced variability results in a standard deviation ( $\sigma $ ) for the threshold voltage ( $\textsf {V}_{\textsf {T}}$ ) of 7 mV for the FinFET when CL/Gate Perimeter = 0.66 and RMS = 0.80 nm, which is 20% greater than that of the GAA NW FET. GER is a less damaging source of variability than metal grain granularity (MGG), line edge roughness (LER), and random dopants (RD) for both devices. When compared to LER variations, $\sigma \textsf {V}_{\textsf {T}}$ due to the GER is 62% and 86% lower for the FinFET and GAA NW FET, respectively. However, although GER affects the FinFET more than the GAA NW FET, the combined variability effect of GER, MGG, LER, and RD ( $\sigma \textsf {V}_{\textsf T, comb}$ ) on the FinFET is 30 mV, a value approximately 50% smaller than that of the GAA NW FET.

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Three cross sections (rectangular, bullet shaped, and triangular), resulting from the fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modeled using in-house 3-D finite-element density-gradient quantum-corrected drift–diffusion and Monte Carlo simulations. We investigate the impact of the shape on ${I}$ – ${V}$ characteristics and on the variability induced by metal grain granularity (MGG), line-edge roughness (LER), and random dopants (RDs) and compared with their combined effect. The more triangular the cross section, the lower the OFF-current, the drain-induced-barrier-lowering, and the subthreshold slope. The ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio is three times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independent of the cross section, the MGG variations are the preeminent fluctuations affecting the FinFETs, with four to two times larger $\sigma {V}_{T}$ than that from the LER and the RDs, respectively. However, the variability induced threshold voltage ( ${V}_{T}$ ) shift is minimal for the MGG (around 2 mV), but ${V}_{T}$ shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-sectional shape has a very small influence in ${V}_{T}$ and OFF-current of the MGG, LER, and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation.

Metal Grain Granularity Study on a Gate-All-Around Nanowire FET

The impact of the metal grain granularity (MGG) variations on subthreshold and ON-current of a 22-nm gate length Si gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is analyzed by assessing five figures-of-merit: threshold voltage ( ${V}_{T}$ ), OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), subthreshold slope (SS) and drain-induced-barrier-lowering at low ( ${V}_{D}={50}$ mV) and high ( ${V}_{D}={1.0}$ V) drain biases, and ON-current variability at the high drain bias. We assume a TiN metal gate with four grain sizes (GS): 10, 7, 5, and 3 nm. The simulations carried out employ: 1) a 3-D finite element (FE) drift-diffusion (DD) simulator with density-gradient (DG) quantum corrections (QC) in the subthreshold region and 2) a 3-D FE Monte Carlo (MC) simulation toolbox with Schrodinger equation QC for the ON-current. We have found that the ${\sigma }{V}_{T}$ due to the MGG variability is 10% higher in the GAA-NW FET (GS of 10 nm) than in a 20-nm gate FinFET. For a GS of 3 nm, the variability becomes comparable between the GAA-NW FET and the FinFET. Comparison against the line-edge-roughness (LER) variability shows that the MGG (GS of 10 nm) affects ${\sigma }{V}_{T}~92$ % more than the LER (root-mean-square height of 0.85nm and correlation length of 20 nm). Finally, the ON-current of the FinFET (GS of 10 nm, ${V}_{D}=\textsf {0.9}$ V) has a 43% higher ${\sigma }{I}_{ \mathrm{\scriptscriptstyle ON}}$ than that of the GAA-NW (GS of 10 nm, ${V}_{D}=\textsf {1.0}$ V) making the GAA-NW FETs a much better solution for sub-10-nm technology nodes.