Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

Abstract

Gate-all-around (GAA) cylindrical Si channel nanowire field-effect transistor (NW-FET) devices have the potential to replace FinFETs in future technology nodes because of their better channel electrostatics control. In this work, 3D TCAD physics-based simulations are performed for the first time to evaluate the potential of NW-FETs at extreme scaling limits of 3 nm using quantum corrected 3D density gradient finite element simulations. Simulations are also performed to study the effects of process-induced variabilities, such as metal grain granularity (MGG) on 3 nm gate length device performance in the sub-threshold region. The importance of MGG induced variability for gate-all-around stacked devices having 3 horizontal nanowires in the 3 nm technology nodes is shown.