Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

Abstract

As predicted, 5nm technology is not going to be ready for production until 2025 and it will be some sort of FinFET (possibly gate-all-around silicon nanowire or similar type of devices). It is time to search for advanced device structures such as nanowires. In this work, TCAD simulations are performed for the first time to evaluate the potential of 1nm gate length cylindrical Si channel nanowire field effect transistors (NW-FET) at extreme scaling limits. Effects of metal grain granularity (MGG) of the gate-all-around (GAA) NW-FET device have been studied to understand variability of the performance metrics such as, the threshold voltage, on-current, off-current, sub-threshold slope and drain induced barrier lowering. It is shown that the gate-all-around NW-FETs have the potential to replace FinFETs in future technology nodes because of their better channel electrostatic control.