Metal Gate Granularity Research Articles

Improved compact model extraction of statistical variability in 5 nm nanosheet transistors and applied to SRAM simulations

In this paper, we look at how artificial neural networks (ANNs) may be used to improve compact model extraction of statistical variability in 5 nm nanosheet transistors (NSTs) and how it can be applied to 6NST-static random access memory (SRAM) simulations. To begin, both the TCAD simulation platform and compact model of 3D n-type and p-type NST have been rigorously validated against the experimental data. The transfer characteristics curves of 1104 NST samples generated by metal gate granularity, random discrete dopants and line edge roughness are used to extract the important figures of merit (FoM) including ON-current (I ON), OFF-current (I OFF), threshold voltage (V TH) and subthreshold slope. Meanwhile, we can collect the main compact model parameters of these NST samples using our automatic extraction technique. Furthermore, a multi-layer ANN engine is trained to anticipate the important compact model parameters by entering FoMs, which significantly speeds up the automatic extraction. When we compare the prediction results to the genuine values, we discover that their correlation coefficients are all larger than 0.99. Finally, we simulated the 6NST-SRAM circuit and obtained its stability variation, with the help of extracted NST variability by the aforementioned speedup techniques.

Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15-22 nm) Nanowire FETs with Various Channel Diameters.

In this study, threshold voltage (Vth) variability was investigated in silicon nanowire field-effect transistors (SNWFETs) with short gate-lengths of 15–22 nm and various channel diameters (DNW) of 7, 9, and 12 nm. Linear slope and nonzero y-intercept were observed in a Pelgrom plot of the standard deviation of Vth (σVth), which originated from random and process variations. Interestingly, the slope and y-intercept differed for each DNW, and σVth was the smallest at a median DNW of 9 nm. To analyze the observed DNW tendency of σVth, a novel modeling approach based on the error propagation law was proposed. The contribution of gate-metal work function, channel dopant concentration (Nch), and DNW variations (WFV, ∆Nch, and ∆DNW) to σVth were evaluated by directly fitting the developed model to measured σVth. As a result, WFV induced by metal gate granularity increased as channel area increases, and the slope of WFV in Pelgrom plot is similar to that of σVth. As DNW decreased, SNWFETs became robust to ∆Nch but vulnerable to ∆DNW. Consequently, the contribution of ∆DNW, WFV, and ∆Nch is dominant at DNW of 7 nm, 9 nm, and 12, respectively. The proposed model enables the quantifying of the contribution of various variation sources of Vth variation, and it is applicable to all SNWFETs with various LG and DNW.

An Accurate Process-Induced Variability-Aware Compact Model-Based Circuit Performance Estimation for Design-Technology Co-Optimization

In sub-10nm FinFETs, Line-edge-roughness (LER) and metal-gate granularity (MGG) are the two most dominant sources of variability and are mostly modeled semi-empirically. In this work, compact models of LER and MGG are used. We show an accurate process-induced variability (PIV) aware compact model-based circuit performance estimation for Design-Technology Co-optimization (DTCO). This work is carried out using an experimentally validated BSIM-CMG model on a 7nm FinFET node. First, we have shown performance bench-marking of LER and MGG models with the state-of-the-art and shown {\textbackslash}4x({\textbackslash}2.3x) accuracy improvement for NMOS(PMOS) in the estimation of device figure of merits (DFoMs). Second, RO and SRAM circuits performance estimation is carried out for LER and MGG variability. Further, {\textbackslash}22\% more optimistic estimate of ({\sigma}/{\mu})\textsubscript{SHM} (Static Hold Margin) compared to the state-of-the-art model with V\textsubscript{DD} variation is shown. Finally, we demonstrate our improved DFoMs accuracy translated to more accurate circuits figure of merits (CFoMs) performance estimation. For worst-case SHM (3({\sigma}/{\mu})\textsubscript{SHM}@VDD=0.75 V) compared to state-of-the-art, dynamic(standby) power reduction by {\textbackslash}73\%({\textbackslash}61\%) is shown. Thus, our enhanced variability model accuracy enables more credible DTCO with significantly better performance estimates.

3-D TCAD Monte Carlo Device Simulator: State-of-the-art FinFET Simulation

This work presents a comprehensive description of an in-house 3D Monte Carlo device simulator for physical mod-eling of FinFETs. The simulator was developed to consider var-iability effects properly and to be able to study deeply scaled devices operating in the ballistic and quasi-ballistic regimes. The impact of random dopants and trapped charges in the die-lectric is considered by treating electron-electron and electron-ion interactions in real-space. Metal gate granularity is in-cluded through the gate work function variation. The capability to evaluate these effects in nanometer 3D devices makes the pre-sented simulator unique, thus advancing the state-of-the-art. The phonon scattering mechanisms, used to model the transport of electrons in pure silicon material system, were validated by comparing simulated drift velocities with available experi-mental data. The proper behavior of the device simulator is dis-played in a series of studies of the electric potential in the device, the electron density, the carrier's energy and velocity, and the Id-Vg and Id-Vd curves.

TCAD-Based Investigation of Statistical Variability Immunity in U-Channel FDSOI n-MOSFET for Sub-7-nm Technology

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

Experimental Validation of Process-Induced Variability Aware SPICE Simulation Platform for Sub-20 nm FinFET Technologies

We propose an experimentally validated physics-based process-induced variability (PIV) aware SPICE simulation framework–enabling the estimation of performance variation due to line-edge-roughness (LER), metal-gate-granularity (MGG), random-dopant-fluctuation (RDF), and oxide-thickness-variation (OTV) at sub-20 nm technology node devices. The framework utilizes LER, RDF, OTV, and MGG defining parameters such as fin-edge correlation coefficient ( $\rho $ ), autocorrelation length ( $\Lambda $ ), grain-size (GS), $\sigma [\text {EOT}]$ , etc. as the inputs, and produces ${I}_{d} $ ,– ${V}_{g}$ distribution of ensemble size 250 as an output. We have validated the framework against 14 nm FinFET experimental data for ${I}_{d}$ ,– ${V}_{g}$ trends as well as for the threshold-voltage ( ${V}_{T}$ ), ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), and subthreshold slope (SS) distributions for a range of device dimensions with a reasonably good match. The worst and the best case ${R}$ square errors are 0.64 and 0.98, respectively, for the validation. The very nature of the proposed framework allows the designers to use it for a vast range of process technologies. Such models are of dual importance, as it enables a PIV aware prediction of circuit-level performance, and provides a platform to estimate PIV parameters efficiently, on-par with sophisticated structural characterization tools.

Nanoscale Transistor Variability Modeling: How Simple Physics Enables a Powerful Prediction Platform

Process-induced variation (PIV) is the major bottleneck for using advanced CMOS technology efficiently. Even though the multigate nature of the fin field effect transistor (FinFET), nano-wire FET (NWFET), and nanosheet FET (NSFET) make the device robust toward the short channel effects (SCEs), unpredictable device-to-device variation caused by unwanted PIV remains a challenge for the designers. In this article, we propose a generic variability model to describe the impact of PIV on performance parameters of advanced devices. The major focus of this article is to demonstrate two independent analytical models capturing the impact of metal gate granularity (MGG) and line edge roughness (LER) on the threshold voltage ( V T ) of FinFET. The proposed model is not only limited to the variability estimation of V T , but also capable of estimating the on-current ( I on), subthreshold slope (SS), and off-current ( I off) distribution due to LER accurately. Both the models are generic enough to be extended to be used for NWFET, and NSFET, and utilizes simple physics and mathematics, therefore, it can be implemented in any platform. The models are 100-1,000 times faster in comparison to the technology CAD (TCAD) simulations, and accuracy is on par with the TCAD results. Such models, when integrated with the existing nominal SPICE setup, the circuit-level performance prediction will be comparable to the experimental results. As the models take process-generated variations as an input to produce corresponding performance variation, it will further enable the co-optimization of the process as well as the circuit performance.

A Simulation Study on Minimizing Threshold Voltage Variability by Optimizing Oxygen Vacancy Concentration Under Metal Gate Granularity

In this work, we discuss the mitigation of threshold voltage ( ${V}_{{TH}}$ ) variability in nanoscale FinFET by exploiting the interaction of oxygen vacancies (OV) against metal gate granularity (MGG). Deposition of a metal gate on high- $\kappa $ dielectric HfO2 is known to generate OV in the dielectric which induces variability in surface potential. A higher workfunction of metal grain increases the probability of OV formation. Interestingly, while a higher workfunction metal grain decreases the surface potential of the channel underneath, the positive charge of OV increases the potential. Therefore, the concentration of OV can be controlled to negate the surface potential variability induced by MGG. We discuss the law of mass action-based concentration models of OV under MGG to analyze this. We also present TCAD simulations supporting the above hypothesis. In our simulations, for 10-nm channel FinFET, MGG-induced $\sigma $ ( ${V}_{{TH}}$ ) can be reduced to ~20 mV from ~35 mV for four-sided planar grains with 8 nm average edge length under the optimal OV concentration.

Improved statistical variability and delay performance with junctionless inserted oxide FinFET

Junctionless inserted oxide FinFET (JL-iFinFET) is presented, its performance metrics are quantified and compared with JL-FinFET and JL-Stacked-Nanowire-FET (JL-SNWFET) respectively for the same foot-print on the wafer. The Random-Dopant-Fluctuation (RDF) and Metal-Gate-Granularity (MGG) are major variability sources in nano-transistors. Impedance Field Method is used to analyze the statistical variability performance of all three structures caused by RDF and MGG. The result shows JL-SNWFET provides superior DC figure-of-merits and 40% less statistical variability than JL-FinFET with a 10% increase in delay and considerable increase in fabrication complexity. The JL-iFinFET offers 30% lesser process-induced threshold voltage and on-current variations compare to JL-FinFET, without deteriorating delay and RF metrics due to its superior electrostatic control over the channel and multi-channel configuration. Fabrication of JL-iFinFET is also possible without adding much complexity in FinFET process it can be a major contender for continued scaling with JL-Transistors (JLTs).

Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology.

Threshold Voltage Variability in Nanosheet GAA Transistors

Nanosheet gate-all-around (GAA) field-effect transistor (NSFET) is a potential replacement for the FinFET at advanced technology nodes owing to better control of short-channel effects and higher drive current. Due to the increased complexity of the GAA stacked structure, new forms of process variability come into the picture, which are dominant over the conventional process variability such as metal gate granularity (MGG) and line edge roughness (LER) for FinFETs. In this article, we show one such process variability called as metal thickness variation (MTV). MTV causes WF variations on the gates of the GAA sheet transistor and results in a significant VT variability. The impact of MTV is studied using an analytical framework. We studied three variants of NSFETs and reported variability in terms of key device design parameters such as intersheet spacing and metal thicknesses. The results presented here help in designing the process flow for a type of NSFET to minimize the VT variability.

Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes

The epitaxially grown SiGe source/drain stressor (e-SiGe) technique has emerged to be a consistent performance booster for advanced devices below the 14 nm technology node. At nanoscale, the omnipresent residual stress is now becoming an important source of variability in advanced VLSI technologies that influence the circuit performance. Also, in deeply-scaled technologies, process and environment variations become other sources of variabilities. In this paper, we study the stress-induced variability in aggressively scaled (at 7 N) Si-channel FinFETs with epitaxially grown SiGe stressors in the source and drain regions. The stress distribution analysis is performed with the help of Technology CAD mechanical stress simulations. At first, we calibrate our simulation results with available experimental data. We generate the stress maps in FinFETs with various scaled dimensions of fin length, height and width. The effects of residual strain/stress on variability due to metal gate granularity (MGG) and random discrete dopant (RDD) in strain-engineered FinFETs (with 50 configurations) have been investigated. Furthermore, the device threshold voltage variation due to RDD and MGG are critically examined. Finally, we calculate the mean and standard deviation of these parameters (QQ plots) to quantify the variability.

Variability Predictions for the Next Technology Generations of n-type SixGe1-x Nanowire MOSFETs.

Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

An accurate expression to estimate the metal gate granularity induced threshold voltage variability in NWFETs

Process variability has been a challenge for advanced transistor technology nodes for logic applications. With the advent of multi-gate architecture, Metal Gate granularity (MGG) has become a significant source of variability. Traditional ways of variability estimation using TCAD simulations are computationally expensive which calls for a compact model. In this paper, a compact form to estimate MGG induced threshold voltage variability in NWFET is proposed. First, a detailed Fourier analysis is used to calculate the electrostatics which resulted in the expression for the barrier height. Second, the statistical moments of the barrier heights are calculated in a closed form expression. A detailed description of the methodology and the derivation is conveyed through this paper along with the justifications for the simplifications and approximations considered. The standard deviations in threshold voltage for various grain sizes are in good agreement with stochastic TCAD simulations. Unlike the conventional TCAD stochastic simulation, the proposed compact form is computationally efficient and also independent of the number of samples (NWFET devices) in finding the variability for a given set of parameters.

Statistical Analysis of Threshold Voltage Variation Using MOSFETs With Asymmetric Source and Drain

Threshold voltage variation is considered to be caused by various factors, such as random dopant fluctuation, surface roughness, metal gate granularity, and so on. Its magnitude ( $\sigma {V}_{\mathrm {th}}$ ) is proportional to the reciprocal of the square root of the gate area in conventional rectangular transistors. In this letter, the statistical analysis of the threshold voltage variation of trapezoidal and octagonal transistors that have asymmetric gate widths at source and drain side was discussed, in addition to the rectangular transistors. From the statistical analysis, it is experimentally demonstrated that $\sigma {V}_{\mathrm {th}}$ is correlated with the gate width at source side ( ${W} _{S}$ ), not average gate width ( ${W} _{\mathrm {ave}}$ ) which determines the gate area. Therefore, it is considered that $\sigma {V}_{\mathrm {th}}$ is characterized by the common parameter of ${W} _{S}$ even if the main factor of the threshold voltage variation would be changed.

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

The random telegraph noise (RTN) time constants, capture (τc) and emission (τe) times, have been extensively used to identify the trap position in the gate oxide by comparing the measured τc-over-τe ratio with the Shockley–Read–Hall (SRH) statistics. However, various factors have been shown to affect the accuracy of the extracted trap depth from the SRH-type models, such as three-dimensional (3D) device electrostatics, atomistic doping, metal gate granularity, and Coulomb energy variation (CEV) of the trap. Focusing on CEV in this work, we assume the trap in gate oxide can be regarded as a floating island and then numerically studied the CEV of the trap with 3D drift-diffusion simulation. Analyzing the simulation data, the extracted trap depth without considering CEV in the SRH statistics are quantitatively compared with the data involved CEV.

Analytical modeling of metal gate granularity based threshold voltage variability in NWFET

Estimation of threshold voltage VT variability for NWFETs has been computationally expensive due to lack of analytical models. Variability estimation of NWFET is essential to design the next generation logic circuits. Compared to any other process induced variabilities, Metal Gate Granularity (MGG) is of paramount importance due to its large impact on VT variability. Here, an analytical model is proposed to estimate VT variability caused by MGG. We extend our earlier FinFET based MGG model to a cylindrical NWFET by satisfying three additional requirements. First, the gate dielectric layer is replaced by Silicon of electro-statically equivalent thickness using long cylinder approximation; Second, metal grains in NWFETs satisfy periodic boundary condition in azimuthal direction; Third, electrostatics is analytically solved in cylindrical polar coordinates with gate boundary condition defined by MGG. We show that quantum effects only shift the mean of the VT distribution without significant impact on the variability estimated by our electrostatics-based model. The VT distribution estimated by our model matches TCAD simulations. The model quantitatively captures grain size dependence with σ(VT) with excellent accuracy (6%error) compared to stochastic 3D TCAD simulations, which is a significant improvement over the state-of- the-art model with fails to produce even a qualitative agreement. The proposed model is 63× faster compared to commercial TCAD simulations.

Impacts of Diameter and Ge Content Variation on the Performance of Si1-xGex p-Channel Gate-All-Around Nanowire Transistors

In this work, the impacts of both nanowire diameter (DNW) and Ge content (%) on the performance of Si1−xGex Gate-all-around nanowire p -channel FETs are investigated. The variations in SiGe Gate-all-around nanowire p -channel FETs induced by DNW variation, Ge content variation, and some stochastic process variations including random dopants fluctuation, gate edge roughness, and metal gate granularity are also evaluated.

Influence of RDF and MGG Induced Variability on Performance of 7 nm Multi-Gate Transistors with Metal/High-k Gate Stack

In this paper impact of two major statistical variability sources Random Dopant Fluctuation (RDF) and Metal Gate Granularity (MGG) on the performance of FinFET, inserted oxide FinFET (iFinFET), and Stacked NanowireFET (SNWFET) is studied and compared using numerical simulations for the same footprint on the wafer. SNWFET and iFinFET show superior immunity toward variability than FinFET because of larger effective width and separated channels from bulk. The conventional controlled channel doping on Punch-Through-Stopper (PTS) doped substrate enhances influence of RDF due to the intrusion of dopants from PTS doping into the channel during the annealing process. Using Super-Steep-Retrograde (SSR) doping profile which is achieved by Oxygen-Insertion (OI) method dopant intrusion from bulk can be reduced, along with this lightly doped channel achieves almost 80% improvement in RDF variability. The SNWFET and iFinFET shows 25% and 17% lower MGG induced threshold voltage (VTH) variability than FinFET because of larger effective gate area. As iFinFET shows almost equal variability with better delay performance than SNWFET it can be a better option at 7 nm technology.

Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET

Metal gate granularity (MGG)-induced threshold voltage variability is the dominant source of variability in FinFETs. The analytical model for MGG-based variability is essential to study its circuit impact. In this paper, we present a novel electrostatics and percolation theory-based analytical model to estimate MGG-induced threshold voltage (VT variability. The model is capable of analyzing realistic grain shape- and position-distributions—demonstrated with random Voronoi grains. The model is benchmarked against stochastic 3-D TCAD simulations to demonstrate excellent accuracy [4% error in $\sigma$ VT]. Furthermore, it shows in excess of $12\times$ improvement in accuracy over existing analytical models. Our model enables a $55\times$ reduction in the computation time in comparison with 3-D stochastic TCAD simulations.