Mesh NoC Research Articles

TEFLON: Thermally Efficient Dataflow-aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a t hermally e fficient data flo w-aware monolithic 3D (M3D) N oC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 42%, 46%, and 45% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores, respectively. TEFLON reduces the peak chip temperature by 25 K and improves the inference accuracy by up to 11% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores.

Evaluation and validation of efficient hierarchical interconnection in multi-processor system on chip

ABSTRACT Multiprocessor system-on-chip (MPSoC) is increasingly used in today’s complicated embedded systems. This paper uses an efficient Hierarchical Interconnection Framework (EHIF) to improve throughput and latency over traditional 3D mesh NoC. The suggested router is hierarchical with one module handling inter-layer communication and intra-layer communication. The EHIF compares well to the traditional 3D mesh in terms of area and power consumption. The EHIF method reduced the execution time without increasing the memory buffer size to optimise time and memory. It achieves a high performance ratio, throughput, low power consumption, latency and delay compared to other methods

SpecMap: An efficient spectral partitioning based static application mapping algorithm for 2D mesh NoCs

SummaryNetwork‐on‐chip (NoC) is adopted as a flexible and effective communication backbone by multiprocessor systems with core counts ranging from a few to hundreds. The performance of NoC based systems greatly rely on the communication between cores when two dependent tasks of an application are mapped to these cores. Hence, application mapping becomes a critical issue in NoC‐based systems as it affects the overall performance of the system. Application mapping aims to reduce the communication among the cores by carefully mapping the highly communicating tasks. Most of the existing static mapping approaches consider only single‐task platforms. In this article, we propose an efficient multi‐task static mapping algorithm called , for regular 2D NoC systems. consists of three stages namely, (i) graph partitioning, (ii) topology clustering, and (iii) mapping. In the graph partitioning stage, accurately identifies and groups the highly communicating tasks based on spectral graph partitioning. Then, the clustering and mapping stages allocate the most communicating tasks in the same or adjacent multi‐tasking cores. It also eliminates the interference between multiple applications by mapping them into different clusters of the NoC network. Simulations of have been conducted on different synthetic and real‐life applications using Gem5 simulator. The simulation results show considerable improvements for SpecMap in terms of communication cost, average network latency, energy consumption, throughput, and execution time as compared to the state‐of‐the‐art algorithms.

Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers

Weighted round-robin (WRR) arbitration provides global fairness in networks-on-chip (NoCs) as opposed to the commonly used round-robin and priority-based arbitration techniques. However, the large number of weights explodes the design space and exacerbates performance (latency-throughput) tuning. Therefore, fast and accurate performance analysis techniques for NoCs are crucial for accelerating design space exploration and accurate pre-silicon evaluation. This article presents the first comprehensive performance analysis technique for NoCs with WRR arbitration and finite buffers. It can handle bursty traffic and is scalable to large NoC sizes. The proposed technique first estimates the probability that a queue is full and uses this result to compute the modified service time and queuing delay. Thorough experimental evaluations with synthetic traffic and real applications show that the proposed analytical model is always more than 10% accurate compared to cycle-accurate simulations. Moreover, the proposed performance analysis technique is five orders of magnitude faster than cycle-accurate simulations for a 16 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 16 mesh NoC.

Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems

The computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous manycore processors, using wormhole mesh (wmesh) Network-on-Chips (NoCs) as the main communication means, and contention block among applications, are increasingly considered to deliver the required computing performance. Most research efforts on software timing analysis have focused on deriving bounds (estimates) to the contention that tasks can suffer when accessing wmesh NoCs. However, less effort has been devoted to an equally important problem, namely,accuratelymeasuring the actual contention tasks generate each other on the wmesh which is instrumental during system validation to diagnose any software timing misbehavior and determine which tasks are particularly affected by contention on specific wmesh routers. In this article, we work on the foundations ofcontention measuringin wmesh NoCs and propose and explain the rationale of agolden metric, called taskPairWise Contention(PWC). PWC allows ascribing the actual share of the contention a given task suffers in the wmesh to each of its co-runner tasks at packet level. We also introduce and formalize aGolden Reference Value(GRV) for PWC that specifically defines a criterion to fairly break down the contention suffered by a task among its co-runner tasks in the wmesh. Our evaluation shows that GRV effectively captures how contention occurs by identifying the actual core (task) causing contention and whether contention is caused by local or remote interference in the wmesh.

Low‐cost regional‐based congestion‐aware routing algorithm for 2D mesh NoC

SummaryGiven the advantages of network‐on‐chips (NoCs), they are rapidly improving to replace other forms of System‐on‐Chip (SoC) designs. Although various factors improve the NoC's performance, many challenges should be addressed when designing an NoC, one of which is congestion and its impacts on performance and efficiency. Hence, numerous routing algorithms have been proposed that contemplate the congestion influences to deal with its complexities. Nevertheless, given the significant impacts of overheads on performance and efficiency, it is crucial to consider them when designing an enhanced NoC. The proposed routing algorithm employs regional traffic information within multiple clusters and has a decent view of the traffic condition when choosing the path to the destination. Each node generates one bit of traffic information and propagates it only when the node is congested, thus preventing the information overhead. Finally, the path diversity parameter is utilized to identify the best route from the source to the destination. The proposed algorithm's results show that the number of received packets, average latency, average throughput, maximum latency, and energy consumption while using different traffic patterns are improved by 10.9%, 35.3%, 15.8%, 43%, and 15.3%, respectively.

MIMO-OFDM LTE system based on a parallel IFFT/FFT on NoC-based FPGA

The growing demand for wireless devices capable of performing complex communication processes has imposed an urgent need for high-speed communication systems and advanced network processors. This paper proposes a hardware workflow developed for the Long-Term Evolution (LTE) communication system. It studies the multiple-input, multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM) LTE system. Specifically, this work focuses on the implementation of the OFDM block that dominates the execution time in high-speed communication systems. To achieve this goal, we have proposed an NoC-based low-latency OFDM LTE multicore system that leverages Inverse Fast Fourier Transform (IFFT) parallel computation on a variable number of processing cores. The proposed multicore system is implemented on an FPGA platform using the ProNoC tool, an automated rapid prototyping platform. Our obtained results show that LTE OFDM execution time is drastically reduced by increasing the number of processing cores. Nevertheless, the NoC’s parameters, such as routing algorithm and topology, have a negligible influence on the overall execution time. The implementation results show up to 24% and 76% execution time reduction for a system having 2 and 16 processing cores compared to conventional LTE OFDM implemented in a single-core, respectively. We have found that a 4×4 Mesh NoC with XY deterministic routing connected to 16 processing tiles computing IFFT task is the most efficient configuration for computing LTE OFDM. This configuration is 4.12 times faster than a conventional system running on a single-core processor.

AI Technology for NoC Performance Evaluation

An on-chip network has become a powerful platform for solving complex and large-scale computation problems in the present decade. However, the performance of bus-based architectures, including an increasing number of IP cores in systems-on-chip (SoCs), does not meet the requirements of lower latencies and higher bandwidth for many applications. A network-on-chip (NoC) has become a prevalent solution to overcome the limitations. Performance analysis of NoC’s is essential for its architectural design. NoC simulators traditionally investigate performance despite they are slow with varying architectural sizes. This work proposes a machine learning-based framework that evaluates NoC performance quickly. The proposed framework uses the linear regression method to predict different performance metrics by learning the trained dataset speedily and accurately. Varying architectural parameters conduct thorough experiments on a set of mesh NoCs. The experiments’ highlights include the network latency, hop count, maximum switch, and channel power consumption as 30-80 cycles, 2-11, $25\mu \text{W}$ , and $240\mu \text{W}$ , respectively. Further, the proposed framework achieves accuracy up to 94% and speedup of up to $2228\times $ .

Design and implementation of asynchronous NOC architecture with buffer-less router

In present days, development in chip technology enables us to incorporate heterogonous cores on one chip. Synchronization and communication between such diverse cores is a major issue. Current Synchronous NOC architecture with buffered router consumes a substantial chip area and Power (clock distribution & I/O buffers). Hence in recent times Buffer-less routers based on Deflective routing are projected as a possible solution, but they suffers from issues like sequential port allocation and slow critical path and also increases the Latency. In this paper we propose 2D 4x4 Asynchronous Mesh NOC architecture with a novel router design using XY routing algorithm. In the proposed router design, we have eliminated the conventional input and output buffers and crossbar switch. We integrated priority encoder and FSM based Arbiter which efficiently solves long critical path issues of conventional Buffer less router by dynamically changing the port priority and hence solves the starvation and Live/Dead lock issue and improves the Area Consumption (i.e., reduced by ≈ 43%). We have used parallel transmission which enables us to improve Speed (by ≈73%) and elimination of I/O buffers reduces the power consumption (≈ 0.56w).

WITHDRAWN: Analysis of advanced BIST methods for three dimensional mesh NOCs router assessment

Certain BIST designing for amazing and heterogeneous systems on a chip is given versatile; different leveled, and flowed power-restricted, embedded memory. The proposed structure contains a BIST designing in a 3-D NOC, low region, low power memory BIST control system, and a consecutive interconnection to them for low coordinating overheads. The plan is 3D advancement due to its straightforwardness; the proposed approach offers heterogeneous memories similarly as the screw up spotting to restrict time multifaceted nature and achieve high test earnestness in power and time prerequisites. Simulation results indicate better results than conventional approach.

Fault-tolerant and Congestion Balanced Routing Algorithm for 2D Mesh NoCs

With the number of cores and nodes in networks-on-chips (NoCs) growing, the node fault occurrence probability is increasing. Although the existing turn model can route packets around the fault area and avoid deadlocks, a large traffic load is generated in the non-rightmost column of the fault region. This paper presents a novel fault-tolerant and congestion balanced (FTCB) routing algorithm that chooses a lower load area as the optimal router path by calculating the maximum path channels to balance traffic load and avoid network congestion. Two methods are proposed to calculate path channels for the fault-free mesh and the fault mesh. The improved odd-even turn rule is introduced to calculate path channels for the fault-free mesh. To balance the network load, free buffer length information is added to path channel calculations, which reflects the global perception. For the non-fault region, we update path channels by using the back formulas from the destination node to the source node. In a fault region, the modified calculation rules of path channels and fault-location odd-even turn rules are given. Compared to the other two related works, the throughput of the FTCB algorithm is improved by 6.92% and 10.7%. Meanwhile, the traffic load of FTCB is decreased to some degree in whole mesh, which shows the FTCB routing algorithm can obviously improve network load balanced, saturation throughput and network latency.

Qualitative Analysis of 3D Routing Algorithms in 3×3×3 Mesh NoC Topology Under Varying Load in Bio-SoC

This article presents a qualitative analysis of a 3D routing algorithm in a 3×3×3 mesh NOC topology. The effect of load variation on throughput, total energy, and maximum delay for different types of routing is observed. The simulation was performed on an Access NOXIM network-on-chip simulator under random traffic conditions. The research involves quality parameters like total packets received, total received flits, global average delay (cycles), global average throughput (flits/cycle), throughput (flits/cycle/IP), max delay (cycles), total energy (J), average power (J/cycle), average power per router (J/cycle), and average waiting time in each buffer. In this article, it was observed after comparing all the routing techniques against the mention parameters the XYZ routing techniques was found perform better followed by West first, and North last, while poor performance was observed against odd-even, negative first, and fully adaptive.

Using Smart Routing for Secure and Dependable NoC-Based MPSoCs

The Internet-of-Things (IoT) boosted the building of computational systems that share computation, communication and storage resources for uncountable types of applications. MultiProcessor System-on-Chip (MPSoC) is a fundamental component of such systems offering large parallelism degree in an ocean of processors and memories connected through one or more Network-on-Chips (NoCs). Therefore, a massive quantity of sensitive information of several applications can share computation and communication resources of the MPSoCs demanding security mechanisms and policies. Besides, the advances of CMOS technologies increases the quantity of static and dynamic faults, requiring a dependable and resilient target architecture, which can be partially fulfilled by an effective and efficient NoC design. This work addresses fault tolerance and security at NoC level with SDR, a routing algorithm that includes the concept of security zones in the MPSoC while providing support for dependable routing avoiding faulty links. The proposed routing algorithm prioritizes communication paths deemed secure in 2D mesh NoCs with deadlock freedom. Experimental results employing realistic workload scenarios based on the NASA Numeric Aerodynamic Simulation (NAS) Parallel Benchmark (NPB) and a fault model for 65nm and 22nm CMOS fabrication technologies demonstrates the scalability, security, and dependability of SDR.

Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in the core graph are uniform and therefore iso-area. This changes for Systems-on-Chip because tasks are mapped to specific blocks and not general-purpose cores. Thus, the area of these specific cores is varying. This requires novel mapping methods. In this paper, we propose a an area-aware cost function for simulated annealing; Furthermore, we advocate the use of nonlinear models as the area is nonlinear: A semi-definite program (SDP) can be used as it is sufficiently fast and shows 20% better area than conventional linear models. Our cost function allows for up to 16.4% better area, 2% better communication (bandwidth times hop distance) and 13.8% better total bandwidth in the network in comparison to the standard approach that accounts for both the network communication and uses cores with varying areas as well.

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

Wireless Network-on-Chip or WiNoC is an alternative to traditional planar on-chip networks. On-chip wireless links are utilized to reduce latency between distant nodes due to its capability to communicate with far-away node within a single hop. This paper analyzes the impact of various routing schemes and the effect of WiNoC sizes on network traffic distributions compared to conventional mesh NoC. Radio hubs (4×4) are evenly placed on WiNoC to analyze global average delay, throughput, energy consumption and wireless utilization. For validation, three various network sizes (8×8, 16×16 and 32×32) of mesh NoC and WiNoC architectures are simulated on cycle-accurate Noxim simulator under numerous traffic load distributions. Simulation results show that WiNoC architecture with the 16×16 network size has better average speedup (∼1.2×) and improved network throughputs by 6.36% in non-uniform transpose traffic distribution. As the trade-off, WiNoC requires 63% higher energy consumption compared to the classical wired NoC mesh.

An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips

As one of the principle patterns of communication technology for 3D-integrated circuit (ICs), the 3D-networks-on-chips (3D-NoCs) have lot of attention from scientific research community. 3D-NoCs has been provided as a propitious solution merging the high parallelism of network-on-chip (NoCs) interconnect paradigm with the high-performance and lower interconnect-power of three-dimensional integration circuits. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a triggered fault-free route forwarding model called TFRF for 3D mesh NoCs without requiring any virtual channels (VCs).TFRF is a deadlock-free scheme by adopting a logic-based routing named TFRF guided by a turn activating rule model. The experimental results show that TFRF possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.

Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithm and Architecture for 3D-NoC of Spiking Neurons

Spiking neural networks (SNNs) are artificial neural network models that more closely mimic biological neural networks. In addition to neuronal and synaptic state, SNNs incorporate the variant time scale into their computational model. Since each neuron in these networks is connected to thousands of others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, very low communication latency is also needed. The 2D-NoC was used as a solution to provide a scalable interconnection fabric in large-scale parallel SNN systems. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. The combination of these two emerging technologies provides a new horizon for IC designs to satisfy the high requirements of low power and small footprint in emerging AI applications. In this work, we first present a comprehensive analytical model to analyze the performance of 3D mesh NoC over variants of different SNN topologies and communications protocols. Second, we present an architecture and a low-latency spike routing algorithm, named shortest path K-means based multicast (SP-KMCR), for three-dimensional NoC of spiking neurons (3DNoC-SNN). The proposed system was validated based on an RTL-level implementation, while area/power analysis was performed using 45nm CMOS technology.

An Internal Schematic View and Simulation of Major Diagonal Mesh Network-on-Chip

NoC is a competent communication for on chip network architectures. It make more efficient the computational and high congestion communication on a single chip. In this paper, we are proposing a NoC topologies, i.e., Major Diagonal Mesh NoC called MD-Mesh NoC. In MD-Mesh NoC the corner of major diagonal linked with each other so that the efficiency of the communication among the corner can be increase. The internal semantic view and register transfer logic (RTL) View has been shown. As number of connections among the nodes increases and number of hopes decreases, performance of packet traversing will get increases. The synthesis and simulation has been done on Vertex 5 FPGA. The hardware parameters like number of slices and memory usage with respect to increase the number of nodes has been calculated on FPGA Vertex 5.

A Comparative Study on Automated Fault—Tolerant Route Discovery with Congestion Control Using TFRF Model for 3-D Network-on-Chips

In recent times, with the capaciousness of on-chip cores endorsed over rapid technology scaling, network-on-chips (NoCs) are turning out to be a crucial element of entire system power performance characteristics. 3D-NoCs has been contributed as an auspicious solution merging the high parallelism of NoCs interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional Integrated Circuits (ICs). For the permanent link faults, an impressive mechanism contemplated is the fault-tolerant routing scheme to provide the performance of the 2-D NoCs. In this article, our proposed Triggered Fault-Free Route Forwarding model (TFRF) for 3-D Mesh NoCs without desiring any virtual channels (VCs) is compared with existing approaches with the intention of validating the performance. The experimental results of our proposed TFRF is evaluated and the performance is enhanced in terms of reliability with minimized overhead and the analytical phase details of the evaluation outcomes.

3D NoC Network using Adaptive Algorithm for 8x8x4 Mesh

This paper presents a qualitative analysis of 3D routing algorithm in 8x8x4 mesh network topology. The traffic distribution in 3D routing algorithm has limited bandwidth along vertical links. Different traffic patterns were used during simulation. The simulation is performed on different traffic pattern. The proposed 3D algorithm has been used to perform better in terms of latency and throughput in comparison with existing routing algorithm. The simulation is done with synthetic traffic pattern in a 8×8×4 3D mesh system design which shows that with existing routing algorithm the network is powerful and steady under various traffic patterns, A weighted adaptive routing algorithm for 8×8×4 3D mesh NoC frameworks with arbitrary traffic pattern reveals to accomplish critical execution improvement in terms of Maximum delay and throughput with existing XYZ routing algorithm. Throughput for WARA at packet injection ratio 0.26 is 0.0009893 and maximum delay at packet injection ratio 0.26 is 976.