Memristor Emulator Research Articles

Charge-controlled grounded memristor emulator circuits based on Arbel-Goldminz cell with variable switching behaviour

Charge-controlled grounded memristor emulator circuits based on Arbel-Goldminz cell with variable switching behaviour

MOSFET-Based Memristor for High-Frequency Signal Processing

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6~\mu \text{W}$ </tex-math></inline-formula> . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates.

Memristive band pass filter chaotic circuit: multistability and control

ABSTRACT This paper studies the influence of an explicit symmetry break on the dynamics of a memristive band pass filter. It is shown that the circuit exhibits complex behaviours. The symmetry break is achieved by considering a memristor emulator with an asymmetric current-voltage characteristic. We describe how the bifurcation sequences, the number and types of coexisting solutions, and the topology of the basins of attraction metamorphose when monitoring both the system parameters and initial conditions. The theoretical results are validated by a series of simulations under PSPICE.

Analysis of Parasitic Effects in a Crossbar in CMOS Based Neuromorphic System for Pattern Recognition Using Memristive Synapses

This paper proposes a complete CMOS realized neuromorphic system for pattern recognition having CMOS-based memristor emulators as synaptic circuits. The crossbar array of the system is modeled by considering the emulator circuit&#x0027;s area to determine the spacing between the interconnects. The interconnect parasitics are obtained from the ANSYS Q3D extractor. Parasitics extracted are also validated using the analytical model. A crossbar array architecture modeled with the extracted parasitic components and the memristor emulator will provide an understanding of the behavior of the crossbar array and can be used to analyze the parasitic effects on various real-time applications. Our analysis shows that as the operating frequency increases, the recognition rate of the neuromorphic system is reduced by 66.67&#x0025; due to the crossbar&#x0027;s parasitics, non-idealities of the neuron, and memristor circuits. The memristor&#x0027;s state, either low or high resistance, significantly affects the system&#x0027;s performance, which is evaluated by the rise time and signal delay. The energy consumed by the CMOS-based memristor emulator synapse for recognizing each pattern is 0.44 &#x00A0;<inline-formula><tex-math notation="LaTeX">$nJ$</tex-math></inline-formula>, which is significantly lower when compared with the previous works. The circuit design and verification are done using 180-nm CMOS technology.

Electronically Tunable Flux-Controlled Resistorless Memristor Emulator

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results.

Compact Charge-Controlled Memristance Simulator with Electronic/Resistive Tunability

The work endeavors to realize a single Voltage Differencing Current Conveyor (VDCC)-based current-controlled memristor emulator with charge-dependent linear memristance function. Such current-controlled memristors closely model the current ([Formula: see text])–voltage ([Formula: see text]) relationship of the popular TiO2-based physical memristor architecture constructed by Hewlett–Packard (HP). The presented emulator circuit comprises only two grounded passive elements and two external MOS transistors along with a VDCC active element and provides the facility of electronic/resistive tunability. It is found through the detailed literature survey that the presented circuit is the most compact design to realize a charge-controlled memristance simulator as compared to any previously reported structure. The designed configuration has been verified through presented simulation results generated using PSPICE based on 0.18[Formula: see text][Formula: see text]m CMOS technology. It has also been validated through relaxation and chaotic oscillators developed using the proposed VDCC-based memristor emulator and output waveforms have been shown. Furthermore, the discussed memristor emulator has been implemented and verified through commercial ICs, AD844 and LM13700.

Wide-band compact floating memristor emulator configuration with electronic/resistive adjustability

The article describes a floating voltage-controlled memristor emulator configuration based on single Dual Z output Voltage Dependent Transconductance Amplifier (DZ-VDTA). The DZ-VDTA is a dual Z output VDTA with provision of X port currents proportional to the differential Z ports’ voltage. The presented memristor employs only two grounded passive elements without any use of bulky external analog multiplier, which is generally required to obtain the voltage dependent memductance expression of memristor. The prime advantages of proposed emulator can also be considered as the provision of electronic and resistance tuning available for controlling the emulated memristor behaviour and its wide operating frequency range from few KHzs to beyond hundred MHz. The designed circuit has been mathematically investigated for the consideration of parasitic elements of DZ-VDTA. Also, the operability of the developed floating memristor emulator has been checked through PSPICE generated simulations. Moreover, proposed memristor based relaxation oscillator has also been developed and verified. Finally, the implementation using LM13700 has been depicted.

Investigation of Power Consumption Effect of Various Memristor Emulators on a Logic Gate

Memristor, also known as memory resistor, is considered as the fourth passive electronic element expressing the relationship between magnetic flux and electric charge. One of the most important features of the memristor is that it has low power consumption. Minimizing power consumption is an important issue in the electronic circuits. However, the fact that the memristor element was not yet fully manufactured has led researchers to design memristor-like emulator circuits. These circuits, which approximate the memristor properties, are realized by combining the other existing electronic elements. In this paper, a basic NAND logic gate is considered and the change in power consumption when using a memristor instead of the standard resistor in the gate circuit is examined. For this purpose, the NAND logic circuit was constituted for four different memristor emulators, and the power consumption values of these circuits were obtained by simulation and experiments. These values are compared with the power consumption values of NAND circuits obtained by using standard resistors equivalent to the memristor resistance. The results clearly show that the memristor gate circuits reduce power consumption compared to standard resistive gate circuits.

MOS-only implementation of memristor emulator circuit

This paper presents an electronically adjustable memristor emulation circuit consisting of only two MOS transistors and a current source. The proposed circuit is topologically very simple, and it allows the memristor emulator to be realized without any external capacitor by using solely the transistor's internal capacitor. As a result of this, the circuit takes up little space on the IC environment. A modification technique based on using a negative immittance converter is used to operate the memristor in locally active region. The validity of the theoretical study is demonstrated by simulation results using the Cadence design environment with 0.18 µm CMOS process and a possible application of the proposed MEC in a chaotic oscillator is presented. The feasibility of the circuit is also verified with experimental results.

Realization of floating triple crossing memristor emulator with dual inflection point static characteristics

Realization of floating triple crossing memristor emulator with dual inflection point static characteristics

Memristor Crossbar-Based Hardware Implementation of Type-2 Fuzzy Membership Function and On-Chip Learning

Utilizing fuzzy techniques, especially fuzzy type-2, is one of the most widely used methods in machine learning to model uncertainty. In addition to algorithm provision, the hardware implementation capability, and proper performance in real-time applications are other challenges. The use of hardware platforms that have biological similarities and are comparable to human neural systems in terms of implementation volume has always been considered. Memristor is one of the emerging elements for the implementation of fuzzy logic based algorithms. In this element, by providing current and selecting the appropriate direction for the applied current, the resistance of the memristor (memristance) will increase or decrease. Various implementations of type-1 fuzzy systems exist, but no implementation of type-2 fuzzy systems has been done based on memristors. In this paper, memristor-crossbar structures are used to implement type-2 fuzzy membership functions. In the proposed hardware, the membership functions can have any shape and resolution. Our proposed implementation of type-2 fuzzy membership function has the potential to learn (On-Chip learning capability regardless of host system). Besides, the proposed hardware is analog and can be used as a basis in the construction of evolutionary systems. Furthermore, the proposed approach is applied to memristor emulator to demonstrate its correct operation.

High Frequency Electronically Tunable Floating Memristor Emulators employing VDGA and Grounded Capacitor

High Frequency Electronically Tunable Floating Memristor Emulators employing VDGA and Grounded Capacitor

A memristive RLC oscillator dynamics applied to image encryption

One of the major challenges in chaos dynamics is the design of simple and realisable electronic circuits capable of complex dynamic behaviours. Our contribution studies the dynamics and implementation of a simple chaotic memristive RLC oscillator circuit of jerky type as well as its application in designing image cryptosystem. The proposed circuit consists of an operational amplifier and an RLC network, comprising a resistor, an inductor, and two capacitors. Considering the crucial role of symmetry in physical, chemical, biological, and mechanical systems, a voltage control memristor emulator is employed to induce symmetry in the proposed circuit. For the dynamic analysis, fourth-order differential equation with exponential nonlinearities is used. Furthermore, standard analysis tools such as Lyapunov spectrum, bifurcation analysis, and phase space trajectories are employed. The phase space is magnetized using four symmetric attractors coexisting for the same set of parameters and different initial conditions indicate the symmetricity of the proposed system. Meanwhile, asymmetric attractor is capable of merging into one symmetric attractor through an attractor-merging bifurcation. Extensive experimental validations of these properties via PSPICE simulations and by using real electronic components are reported. Finally, the chaotic sequences emanating from the proposed oscillator are exploited to design an encryption algorithm that is subsequently validated via simulations and standard image security analysis with prominent outcomes in terms of very low encryption time (0.0746s for 128 × 128 colour image), mean entropy of 7.999 and mean NPCR of 99.62% just to name a few.

Implementation of Hodgkin-Huxley Neuron Model With the Novel Memristive Oscillator

In this brief, in order to simplify the implementation of the classical Hodgkin-Huxley neuron (HH) model, a novel floating memristor emulator is introduced, which consists of four electronic components and can be considered the simplest implementation in the existing literature. Firstly, the schematic diagrams of the proposed novel HH neuron-based memristive oscillator is presented, and the working mechanism and the bursting phenomenon of which are analyzed. Then, the simulation model of the proposed memristive oscillator emulator is developed in MULTISIM using several off-the-shelf components, which is used to implement a HH neuron model. Moreover, the electrical characteristics of it are examined. In particular, the relationship between the ion channels concentration and the variable voltages of the neuron model is described in detail. Simulation results confirm that the proposed model demonstrates rich bursting oscillation behaviors which is more suitable for simulating the giant squid axon compared to the existing model in the literature, which can be utilized to transmit the neuron information and establish the neural network.

Memristor emulation and analog application using differential difference current conveyor of CC-II in CMOS technology

Memristors have drawn a significant widespread attention from the research community since past decade due to their high-speed operational potential in analog applications. However, it has been difficult to achieve the memristor behavior directly from solid state solution and state of the art. This work presents a novel emulator design to mimic the memristor behavior. A generic and simple emulator circuit for a voltage controlled memristor is presented using a differential difference current conveyor, which is based on a versatile second-generation current conveyor methodology. Although, the voltage-controlled memristor models are of great importance, no significant research has been done to build emulator circuits for this type of memristor. A high-speed low power DDCC in 130 nm RF-CMOS process has been designed and functional simulations have been performed on SPICE environment using Advanced Design System (Keysight Technology). Proposed DDCC then implements the memristor operation with compatible specifications. Finally, the memristor operation and potential has been verified by its application in high speed active filter operations. A universal biquad section has been presented which employs the designed memristor emulator, with 30 mW of power dissipation with ± 1.5 V supply.

A novel memristor emulator design and universal biquad filter application using second generation high swing differential current conveyor transconductance amplifier in 130 nm CMOS process

Memristors have drawn a significant wide spread attention from the research community since past decade due to their high-speed operational potential in analog applications. However, it has been difficult to achieve the memristor behavior directly from solid state solution and state of the art. This work presents a novel emulator design to mimic the memristor behavior. A generic and simple emulator circuit for a voltage controlled memristor is presented using a differential difference current conveyor transconductance amplifier (DDCCTA), which is based on a versatile second-generation current conveyor methodology. A high-swing (up to ±600 mA at the output) and low power implementation design effort for DDCCTA is kept in 130 nm RF-CMOS process with dual power supply mode. The functional simulations have been performed in SPICE environment using Advanced Design System (Keysight Technology), which showed a good alignment to the memristor emulator’s I-V characteristic at 1 KHz and 10 KHz. Proposed DDCCTA then implements the memristor operation with compatible specifications. Finally, the memristor operation and potential has been verified by its application in high-speed active filter operations. A universal biquad section has been presented which employs the designed memristor emulator, with 30 mW of power dissipation with ±1.5 V supply.

A novel current-controlled memristor-based chaotic circuit

In this paper, a novel third-order autonomous memristor-based chaotic circuit is proposed. The circuit has simple topology and contains only four elements including one linear negative impedance converter-based resistor, one linear capacitor, one linear inductor, and one nonlinear current-controlled memristor. Firstly, the voltage-current characteristic analysis of the memristor emulator for different driving amplitudes and frequencies are presented. With dimensionless system, the symmetry, equilibrium point and its stability are analysed. It is shown that the system has two unstable saddle-foci and one unstable saddle. A set of typical parameters are chosen for the generation of chaotic attractor. Differing from the common period-doubling bifurcation route in smooth dynamical systems, this memristive system shows abrupt transition from the coexisting period-1 limit cycles to robust chaos when varying system parameters. Various dynamical behaviors are analysed using the numerical simulations and circuit verifications.

A simple time-delay memristor and its application in 2D HR neuron model

Since the concept of memristor was proposed, the memristor, as the fourth-generation electronic component, has attracted great attention from researchers. Memristors can be used not only for nonvolatile memory but also to mimic the behavior of nervous system. The inherent nonlinearity of memristor makes it valuable in nonlinear circuits. Since it is still difficult to realize the commercial application of memristors at present, designing suitable memristor models can play a guiding role in practical application. This work proposes a novel memristor model with a time-delay state variable. The proposed memristor cannot only generate pinched hysteresis loop under periodic signal excitation, but also can generate chaotic current or even hyperchaotic current under DC voltage. The nonlinear dynamics of the proposed time-delay memristor are studied by phase portraits, bifurcation diagram and Lyapunov exponents. Furthermore, the proposed memristor is used in the HR neuron model to study neuronal electrical activities with electromagnetic induction. Multiple firing patterns of the memristive neuron can be generated such as periodic, bursting and chaotic. Finally, the memristor emulator circuit and the HR neuron model circuit are designed and simulated by Pspice.

Simple flux‐controlled grounded memristor emulator circuits based on current follower

Simple flux‐controlled grounded memristor emulator circuits based on current follower

A Novel Passive Circuit Emulator for a Current-Controlled Memristor

A memristor is an electrical element, which has been conjectured in 1971 to complete the lumped circuit theory. Currently, researchers use memristor emulators through diodes, inductors, and other passive (or active) elements to study circuits with possible attractors, chaos, and ways of implementing nonlinear transformations for low-voltage novel computing paradigms. However, to date, such passive memristor emulators have been voltage-controlled. In this study, a novel circuit realization of a passive current-controlled passive inductorless emulator is established. It overcomes the lack of passive current-controlled memristor commercial devices, and it can be used as part of more sophisticated circuits. Moreover, it covers a gap in the state of the art because, currently, only passive circuit voltage-controlled memristor emulators and active current-controlled emulators have been developed and used. The emulator only uses two diodes, two resistors, and one capacitance and is passive. The formal theory and simulations validate the proposed circuit, and experimental measurements were performed. The parameter conditions of numerical simulations and experiments are consistent. Simulations were performed with an input current amplitude of 15 mA and frequencies of up to 3 kHz and measurements were carried out with an input current amplitude of 0.74 mA and frequency of 1.5 kHz in order to compare with the state of the art.