Memristor-based Circuits Research Articles

A bistable memristor-based circuit system and its implementation

A bistable memristor-based circuit system and its implementation

Memristor-based neural network circuit of pavlov associative memory with dual mode switching

There are many learning modes in associative memory, but most of memristor-based Pavlov associative memory circuits only have a single mode. A learning circuit that can realize Pavlov associative memory with dual-mode switching is designed and verified by the simulation results. The designed circuit consists of the auditory (visual) synapse, auditory (visual) control voltage module and auditory (visual) inhibition module. This paper considers two different learning modes, auditory mode and visual mode. The modes can run not only separately but also alternately. Besides, the paper also considers the inhibition relationship between learning modes and reflects the relationship by adjusting the influence of mode switching period on the learning speed of modes. As a widespread phenomenon in the natural world, mode inhibition of associative memory can be regarded as a psychological process of living things under different external stimulus. Mode inhibition is an interesting subject, which can allow the artificial neural network to mimic more realistic situations of memory. The dual mode switching is an essential part of life, which can provide more references for the practical application of memristor.

Self-organizations with fast-slow time scale in a memristor-based Shinriki’s circuit

The structure of complex oscillations with two time scales generated by a novel memristor-based Shinriki’s circuit is studied in detail. Employing the stability phase diagrams, we identify the parameter regions of mixed-mode oscillations (MMOs) produced by each state variable, and classify the fast and slow properties of state variables according to the characteristics of these MMOs. Additionally, we exhibit the self-organizations of phases and describe how they are interconnected and how their complexity unfolds with control parameters varying. For several parameter combinations, in addition to recently reported shrimp-shaped cascades and “eye” of chaos, two kinds of interesting self-organizations, the shrimp cascade covered by four distinct numbers of peaks and “eye” of anti-chaos, are also discovered. A significant feature of these structures indicates that the fast-slow dynamics of the system depend not only on the state variables but also strongly on the parameter interval. The results of theoretical analyses obtained are verified by the Multisim simulation experiments. This paper will contribute to understanding the profound dynamical behaviors of the memristor-based circuit and open the possibility of studying hitherto unobserved phenomena.

Coexisting Infinite Orbits in an Area-Preserving Lozi Map.

Extreme multistability with coexisting infinite orbits has been reported in many continuous memristor-based dynamical circuits and systems, but rarely in discrete dynamical systems. This paper reports the finding of initial values-related coexisting infinite orbits in an area-preserving Lozi map under specific parameter settings. We use the bifurcation diagram and phase orbit diagram to disclose the coexisting infinite orbits that include period, quasi-period and chaos with different types and topologies, and we employ the spectral entropy and sample entropy to depict the initial values-related complexity. Finally, a microprocessor-based hardware platform is developed to acquire four sets of four-channel voltage sequences by switching the initial values. The results show that the area-preserving Lozi map displays coexisting infinite orbits with complicated complexity distributions, which heavily rely on its initial values.

Coexisting hidden and self-excited attractors in a locally active memristor-based circuit.

This paper presents a chaotic circuit based on a nonvolatile locally active memristor model, with non-volatility and local activity verified by the power-off plot and the DC V-I plot, respectively. It is shown that the memristor-based circuit has no equilibrium with appropriate parameter values and can exhibit three hidden coexisting heterogeneous attractors including point attractors, periodic attractors, and chaotic attractors. As is well known, for a hidden attractor, its attraction basin does not intersect with any small neighborhood of any unstable equilibrium. However, it is found that some attractors of this circuit can be excited from an unstable equilibrium in the locally active region of the memristor, meaning that its basin of attraction intersects with neighborhoods of an unstable equilibrium of the locally active memristor. Furthermore, with another set of parameter values, the circuit possesses three equilibria and can generate self-excited chaotic attractors. Theoretical and simulated analyses both demonstrate that the local activity and an unstable equilibrium of the memristor are two reasons for generating hidden attractors by the circuit. This chaotic circuit is implemented in a digital signal processing circuit experiment to verify the theoretical analysis and numerical simulations.

Memristor-based hyper-chaotic circuit for image encryption* *Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB1306600), the National Natural Science Foundation of China (Grant Nos. 62076207 and 62076208), and the Fundamental Science and Advanced Technology Research Foundation of Chongqing, China (Grant Nos. cstc2017jcyjBX0050).

The memristor is a kind of non-linear element with memory function, which can be applied to chaotic systems to increase signal randomness and complexity. In this paper, a new four-dimensional hyper-chaotic system is designed based on a flux controlled memristor model, which can generate complex chaotic attractors. The basic dynamic theory analysis and numerical simulations of the system, such as the stability of equilibrium points, the Lyapunov exponents and dimension, Poincare maps, the power spectrum, and the waveform graph prove that it has rich dynamic behaviors. Then, the circuit implementation of this system is established. The consistency of simulation program with integrated circuit emphasis (SPICE) simulation and numerical analysis proves the ability to generate chaos. Finally, a new image encryption scheme is designed by using the memristor-based hyper-chaotic system proposed in this paper. The scheme involves a total of two encryptions. By using different security analysis factors, the proposed algorithm is compared with other image encryption schemes, including correlation analysis, information entropy, etc. The results show that the proposed image encryption scheme has a large key space and presents a better encryption effect.

Coexisting Multi-Dynamics of a Physical SBT Memristor-Based Chaotic Circuit

This paper presents a new physical [Formula: see text] (SBT) memristor-based chaotic circuit. The equilibrium point and the stability of the chaotic circuit are analyzed theoretically. This circuit system exhibits multiple dynamics such as stable point, periodic cycle and chaos by means of Lyapunov exponents spectra, bifurcation diagrams, Poincaré maps and phase portraits, when the initial state or the circuit parameter changes. Specially, the circuit system exhibits coexisting multi-dynamics. This study provides insightful guidance for the design and analysis of physical memristor-based circuits.

Memristor‐based stateful logic gates for multi‐functional logic circuit

Memristor-based stateful logic circuits can perform logic operations and logic value storage, which creates an intriguing opportunity for the implementation of an advanced computational architecture. This study proposes a novel memristor-based stateful logic implementation. Specifically, the presented approach is capable of realising two-input or multi-input AND, OR, NAND and NOR operations, and single-input COPY and NOT operations. In each logic gate, non-volatile resistances of memristor are used as input and output states, thus enabling stateful logic operations. Compared with several existing approaches, the proposed method can lead to a multi-functional stateful logic circuit, performing multiple stateful logic operations simultaneously. The effectiveness of the proposed design is demonstrated with the simulation results of MATLAB and SPICE.

Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits.

Nonlinear dynamics in non-volatile locally-active memristor for periodic and chaotic oscillations* *Project supported by the National Natural Science Foundation of China (Grant No. 61771176).

Complexity and abundant dynamics may arise in locally-active systems only, in which locally-active elements are essential to amplify infinitesimal fluctuation signals and maintain oscillating. It has been recently found that some memristors may act as locally-active elements under suitable biasing. A number of important engineering applications would benefit from locally-active memristors. The aim of this paper is to show that locally-active memristor-based circuits can generate periodic and chaotic oscillations. To this end, we propose a non-volatile locally-active memristor, which has two asymptotically stable equilibrium points (or two non-volatile memristances) and globally-passive but locally-active characteristic. At an operating point in the locally-active region, a small-signal equivalent circuit is derived for describing the characteristics of the memristor near the operating point. By using the small-signal equivalent circuit, we show that the memristor possesses an edge of chaos in a voltage range, and that the memristor, when connected in series with an inductor, can oscillate about a locally-active operating point in the edge of chaos. And the oscillating frequency and the external inductance are determined by the small-signal admittance Y(iω). Furthermore, if the parasitic capacitor in parallel with the memristor is considered in the periodic oscillating circuit, the circuit generates chaotic oscillations.

Forward and reverse asymmetric memristor-based jerk circuits

To better demonstrate the asymmetric properties of physical memristive devices, this paper presents an asymmetric memristor emulator that is constructed by an asymmetric diode-bridge cascaded with a parallel resistor–capacitor (RC) filter. By introducing this emulator into a third-order jerk circuit in both forward and reverse ways, this paper constructs two types of asymmetric memristor-based jerk circuits. The two circuits don’t have symmetry themselves, but they are symmetric with each other. By using multiple numerical methods, parameter-associated bifurcation behaviors and initial-associated coexisting behaviors are revealed. Complex dynamics can be thereby observed from these two circuits, including period, chaos, periodic bubble, chaotic bubble, period-doubling bifurcation, antimonotonicity, and extreme event. Furthermore, Multisim circuit simulation models are established and the measured results validate the numerically simulated ones.

Memristor-Based Analog Recursive Computation Circuit for Linear Programming Optimization

Linear programming optimization is central to engineering designs, logistics management, and decision-making in every sector of the economy. Traditional hardware using CPU and GPU platforms for this purpose is severely limited by the scaling of the transistor technology. In this article, we design an analog in-memory computation circuit for accelerating linear programming optimization problems. The scheme includes a memristive crossbar array and analog peripheral circuits that do not require DAC/ADC between each algorithm iteration. In addition, several key parameters related to nonideal device characteristics and interconnect parasitics are discussed for providing practical guidelines. Furthermore, three design schemes are proposed to alleviate the computation error caused by the interconnect resistance for a large-scale crossbar array implementation. Optimal design parameters are quantified under a given number of array size and memristive resistance. Finally, the proposed hardware accelerator and error mitigation techniques are applied to six real-world power system optimization problems. The results show that the average error of generator power and the overall cost is less than 3%. It is demonstrated that the proposed accelerator achieves area, delay, and energy consumption reductions of $\sim 151\times $ , $\sim 33\times $ , and $\sim 21\times $ , respectively, compared with the CMOS digital circuits at the 16-nm technology node for a $1000\times1000$ array with 6-bit precision.

Complex Dynamics of a Novel Chaotic System Based on an Active Memristor

On the basis of the bistable bi-local active memristor (BBAM), an active memristor (AM) and its emulator were designed, and the characteristic fingerprints of the memristor were found under the applied periodic voltage. A memristor-based chaotic circuit was constructed, whose corresponding dynamics system was described by the 4-D autonomous differential equations. Complex dynamics behaviors, including chaos, transient chaos, heterogeneous coexisting attractors, and state-switches of the system were analyzed and explored by using Lyapunov exponents, bifurcation diagrams, phase diagrams, and Poincaré mapping, among others. In particular, a novel exotic chaotic attractor of the system was observed, as well as the singular state-switching between point attractors and chaotic attractors. The results of the theoretical analysis were verified by both circuit experiments and digital signal processing (DSP) technology.

SPICE model of HP-memristor using PWL window function for neuromorphic system design application

The nanoscale memristor device SPICE modeling is significant for memristive circuits and neuromorphic system design applications. In this paper, a novel modified piece-wise linear (PWL) window function proposed for the nonlinear property of the memristor SPICE model. The PWL window function used here can address the shortcoming of the parabola and Heaviside- step function based typical window functions proposed in the literature, those are established by symmetrical functions. However, in most of the typical window functions, the monotonically increasing and the asymmetrical functions have not been addressed. Also, using this PWL-window function based memristor model, a binary-weighted memristor-based artificial synaptic circuit has been designed. The performance of the device model demonstrated by the efficiency of designed artificial synapse sensitivity to the external input signal.

Designing pulse-coupled neural networks with spike-synchronization-dependent plasticity rule: image segmentation and memristor circuit application

Pulse-coupled neural network (PCNN) is a powerful unsupervised learning model with many parameters to be determined empirically. In particular, the weight matrix is invariable in the iterative process, which is inconsistent with the actual biological system. Based on the existing research foundation of biology and neural network, we propose a spike-synchronization-dependent plasticity (SSDP) rule. In this paper, the mathematical model and algorithm of SSDP are presented. Furthermore, a novel memristor-based circuit model of SSDP is designed. Finally, experimental results demonstrate that SSDP has greatly improved the image processing capabilities of PCNN.

Antiphase synchronization and central symmetrical antiphase synchronization in magnetic field coupled circuits

The dynamics of memristor-based RLC circuit is explored on the effects of magnetic field coupling through a transformer in the circuit. With the increasing strength of magnetic field coupling, the two coupled RLC circuits firstly break the reflectional symmetry by transiting from double-scroll attractors to single-scroll attractors and then break the translational symmetry with two attractors in different sizes and shapes. The two single-scroll attractors are locked in antiphase synchronous states for positive magnetic field coupling while transit to a new kind of dynamic regime, named as central symmetrical antiphase synchronization (CSAS) for negative magnetic field coupling. Moreover, the single-scroll attractors in inphase synchronization or in CSAS may coexist with asynchronous states in some interval of coupling strength. The dynamics of the anti-synchronization and the CSAS of the coupled memristor-based circuits have potential applications in nonvolatile memories, neuromorphic devices to simulate learning, adaptive and spontaneous behaviors.

Bifurcation analyses and hardware experiments for bursting dynamics in non-autonomous memristive FitzHugh-Nagumo circuit

In this paper, a non-autonomous memristive FitzHugh-Nagumo (FHN) circuit is constructed using a second-order memristive diode bridge with LC network. For convenience of circuit implementation, an AC voltage source is adopted to substitute the original AC current stimulus. Stimulated by the slowly varying AC voltage source, the number, locations and stabilities of the equilibrium points slowly evolve with the time, which are thus indicated as the AC equilibrium points. Different sequences of fold and/or Hopf bifurcations are encountered in a full period of time series evolutions, leading to various kinds of chaotic or periodic bursting activities. To figure out the related bifurcation mechanisms, the fold and Hopf bifurcation sets are mathematically formulated to locate the critical bifurcation points. On this basis, the transitions between the resting and repetitive spiking states are clearly illustrated by the time series of the AC equilibrium points and state variables, from which Hopf/subHopf, Hopf/Hopf, and Hopf/fold bursting oscillations are identified in the specified parameter regions. Finally, based on a fabricated hardware circuit, the experimental measurements are executed. The results verify that the presented memristive FHN circuit indeed exhibits complex bursting activities, which enriches the family of memristor-based FHN circuits with bursting dynamics.

A memristor-based circuit design for generalization and differentiation on Pavlov associative memory

The traditional Pavlov associative memory contains the process of learning and forgetting, which correspond to the reinforcement and extinction in classical conditional reflex respectively. In fact, besides reinforcement and extinction, classical conditional reflex also contains generalization and differentiation. In this paper, a memristor-based circuit is designed to implement generalization and differentiation based on Pavlov associative memory. This circuit can respond to one kind of conditional stimulus after the initial learning, then when another similar stimulus is applied to the circuit, the circuit responds similarily, this is the phenomenon of generalization. To make the circuit be sufficiently cognizant of these two similar stimuli and ultimately distinguish them, a special training method, which selectively reinforces one stimulus while inhibits another similar stimulus, is used to train the whole circuit. As a result, when these two similar stimuli are applied to the circuit separately again, it can respond to them differently. This is the phenomenon of differentiation. Finally, the correctness of implementing these functions described above are demonstrated by simulation results in PSPICE.

Hyperchaotic Behavior in the Novel Memristor-Based Symmetric Circuit System

A novel five-dimensional (5D) memristor-based symmetric circuit, which consists of two symmetric capacitors, two symmetric inductors and only one memristor is presented in this article. The multivariable first order and multivariable second order polynomial functions are used for the internal state function of the memristor respectively. Theoretical and simulation analyses of the novel memristive circuit are investigated using equilibrium points, phase portraits, bifurcation diagrams and Lyapunov exponent spectra, etc. Complex chaotic behaviors are observed and analyzed through simulation results. The first order internal state function memristor-based symmetric circuit system can only exhibit chaotic behavior whereas the second order internal state function memristor-based symmetric circuit system can generate not only chaotic attractors, but also hyperchaotic attractors in proper parameters.

Comprehensive Read Margin and BER Analysis of One Selector-One Memristor Crossbar Array Considering Thermal Noise of Memristor With Noise-Aware Device Model

It can never be overemphasized the importance of understanding noise in electronics. However, it has not been deeply considered in memristor-based circuits and systems, while there have been tons of efforts to utilize the memristors to improve the present computing system. This article presents comprehensive read margin and bit-error-rate (BER) analyses, where the noise contributions from the memristor and selector devices are fully considered. The analyses provide an accurate BER estimation of a huge crossbar array (CBA) based on a I-V measurement of a single device, which considerably accelerates the engineering time for device and system by eliminating full-array level noise simulations from the iteration loop. Generic noise-aware device models of memristor and selector are also proposed in this paper, and the validity of the analyses is verified from CBA based on the device models.