Memristor Crossbar Array Research Articles

Programmable Threshold Logic Implementations in a Memristor Crossbar Array.

In this study, we demonstrate the implementation of programmable threshold logics using a 32 × 32 memristor crossbar array. Thanks to forming-free characteristics obtained by the annealing process, its accurate programming characteristics are presented by a 256-level grayscale image. By simultaneous subtraction between weighted sum and threshold values with a differential pair in an opposite way, 3-input and 4-input Boolean logics are implemented in the crossbar without additional reference bias. Also, we verify a full-adder circuit and analyze its fidelity, depending on the device programming accuracy. Lastly, we successfully implement a 4-bit ripple carry adder in the crossbar and achieve reliable operations by read-based logic operations. Compared to stateful logic driven by device switching, a 4-bit ripple carry adder on a memristor crossbar array can perform more reliably in fewer steps thanks to its read-based parallel logic operation.

3D-integrated multilayered physical reservoir array for learning and forecasting time-series information

A wide reservoir computing system is an advanced architecture composed of multiple reservoir layers in parallel, which enables more complex and diverse internal dynamics for multiple time-series information processing. However, its hardware implementation has not yet been realized due to the lack of a high-performance physical reservoir and the complexity of fabricating multiple stacks. Here, we achieve a proof-of-principle demonstration of such hardware made of a multilayered three-dimensional stacked 3 × 10 × 10 tungsten oxide memristive crossbar array, with which we further realize a wide physical reservoir computing for efficient learning and forecasting of multiple time-series data. Because a three-layer structure allows the seamless and effective extraction of intricate three-dimensional local features produced by various temporal inputs, it can readily outperform two-dimensional based approaches extensively studied previously. Our demonstration paves the way for wide physical reservoir computing systems capable of efficiently processing multiple dynamic time-series information.

Processing‐in‐memory based multilateration localization in wireless sensor networks using memristor crossbar arrays

SummaryMost of the multilateration algorithms for object localization rely heavily on matrix multiplication for calculating the precise location of the target from all the reference points in a 3D domain. A significant disadvantage is that performing matrix multiplication can be computationally expensive, particularly for larger matrices, leading to slower performance and longer processing times. In this article, we propose a Processing‐in‐Memory (PIM) based localization approach for multilateration using a memristor crossbar array for performing faster matrix multiplication. The experiments were conducted on real‐time data collected through ultra‐wideband (UWB) chip. The simulation results demonstrate that the proposed model is around 50% faster than the fastest known localization algorithm considered for evaluation and exhibits an average of 55% improvement in localization accuracy.

Self-Rectifying All-Optical Modulated Optoelectronic Multistates Memristor Crossbar Array for Neuromorphic Computing.

Researching optoelectronic memristors capable of integrating sensory and processing functions is essential for advancing the development of efficient neuromorphic vision. Here, we experimentally demonstrated an all-optical controlled and self-rectifying optoelectronic memristor (OEM) crossbar array with the function of multilevel storage under light stimuli. The NiO/TiO2 device exhibits an ultrahigh (>104) rectifying ratio (RR) thus overcoming the presence of sneak current. The reversible conductance modulation without electric signal involvement provides a novel way to realize ultrafast information processing. The proposed OEM array realized synaptic functions observed in the human brain, including long-term potentiation (LTP), long-term depression (LTD), paired-pulse facilitation (PPF), the transition from short-term memory (STM) to long-term memory (LTM), and learning experience behaviors successfully. The authors present a novel OEM crossbar that possesses complete light-modulation capabilities, potentially advancing the future development of efficient neuromorphic vision.

Towards Energy-Efficient Spiking Neural Networks: A Robust Hybrid CMOS-Memristive Accelerator

Spiking Neural Networks (SNNs) are energy-efficient artificial neural network models that can carry out data-intensive applications. Energy consumption, latency, and memory bottleneck are some of the major issues that arise in machine learning applications due to their data-demanding nature. Memristor-enabled Computing-In-Memory (CIM) architectures have been able to tackle the memory wall issue, eliminating the energy and time-consuming movement of data. In this work we develop a scalable CIM-based SNN architecture with our fabricated two-layer memristor crossbar array. In addition to having an enhanced heat dissipation capability, our memristor exhibits substantial enhancement of 10% to 66% in design area, power and latency compared to state-of-the-art memristors. This design incorporates an inter-spike interval (ISI) encoding scheme due to its high information density to convert the incoming input signals into spikes. Furthermore, we include a time-to-first-spike (TTFS) based output processing stage for its energy-efficiency to carry out the final classification. With the combination of ISI, CIM and TTFS, this network has a competitive inference speed of 2μs/image and can successfully classify handwritten digits with 2.9mW of power and 2.51pJ energy per spike. The proposed architecture with the ISI encoding scheme can achieve ∼10% higher accuracy than those of other encoding schemes in the MNIST dataset.

Realistic Chest X‐Ray Image Synthesis via Generative Network with Stochastic Memristor Array for Machine Learning‐Based Medical Diagnosis

AbstractArtificial Intelligence (AI) technology has attracted tremendous interest in the medical community, from image analysis to lesion diagnosis. However, progress in medical AI is hampered by a lack of available medical image datasets and labor‐intensive labeling processes. Here, it is demonstrated that a large number of annotated, realistic chest X‐ray images can be generated using a state‐of‐the‐art generative adversarial network (GAN) that exploits noise produced by stochastic in‐memory computing of memristor crossbar arrays. Memristors based on polymer film with high thermal resistance can increase the stochasticity of the tunneling distance for randomly ruptured conductive filaments via excessive Joule heating, thus generating true random numbers required for creating naturally diverse images in GAN. Using StyleGAN2‐adaptive discriminator augmentation (ADA), high‐quality chest X‐ray images with and without pneumothorax are successfully augmented while maintaining a good Frechet inception distance score. The results provide a cost‐effective solution for preparing privacy‐sensitive medical images and labeling to develop innovative medical AI algorithms.

Implementation of Convolutional Neural Networks in Memristor Crossbar Arrays with Binary Activation and Weight Quantization.

We propose a hardware-friendly architecture of a convolutional neural network using a 32 × 32 memristor crossbar array having an overshoot suppression layer. The gradual switching characteristics in both set and reset operations enable the implementation of a 3-bit multilevel operation in a whole array that can be utilized as 16 kernels. Moreover, a binary activation function mapped to the read voltage and ground is introduced to evaluate the result of training with a boundary of 0.5 and its estimated gradient. Additionally, we adopt a fixed kernel method, where inputs are sequentially applied to a crossbar array with a differential memristor pair scheme, reducing unused cell waste. The binary activation has robust characteristics against device state variations, and a neuron circuit is experimentally demonstrated on a customized breadboard. Thanks to the analogue switching characteristics of the memristor device, the accurate vector-matrix multiplication (VMM) operations can be experimentally demonstrated by combining sequential inputs and the weights obtained through tuning operations in the crossbar array. In addition, the feature images extracted by VMM during the hardware inference operations on 100 test samples are classified, and the classification performance by off-chip training is compared with the software results. Finally, inference results depending on the tolerance are statistically verified through several tuning cycles.

Demonstration of a novel majority logic in a memristive crossbar array for in-memory parallel computing.

A memristive crossbar array can execute Boolean logic operations directly within the memory, which is highly noteworthy as it addresses the data bottleneck issue in traditional von Neumann computing. Although its potential has been widely demonstrated, achieving practical levels of operational reliability and computational efficiency remains a challenge. Here, we introduce a three-input majority logic gate supported by near-memory operations, serving as a universal gate and achieving both robust reliability and high efficiency in versatile logic operations. We fabricated a highly reliable HfOx-based memristive array, incorporating a series resistor to increase the reset voltage of the memristor, thereby increasing the operational voltage margin of the gate operation. This ensured reliable operation of the majority gate, resulting in successful experimental proof of combined 1-bit full adder and subtractor operations performed in 5 steps using 7 cells. Additionally, we propose that an N-bit parallel prefix adder (PPA) operation is possible in O(log2 N) steps, by taking advantage of the parallel operation capability of the majority gate. This achieves 8.5× higher spatiotemporal efficiency than the previously reported NOR-based logic system in 64-bit adder operation. Moreover, as N increases, the spatiotemporal efficiency further improves, which significantly enhances the applicability of memristive logic-in-memory.

Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays

Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays

Memristor-Inspired Digital Logic Circuits and Comparison With 90-/180-nm CMOS Technologies

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{2}}$</tex-math> </inline-formula> O <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\text{3}}$</tex-math> </inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Heterogeneous density-based clustering with a dual-functional memristive array.

In the big data era, the requirement for data clustering methods that can handle massive and heterogeneous datasets with varying distributions increases. This study proposes a clustering algorithm for data sets with heterogeneous density using a dual-mode memristor crossbar array for data clustering. The array consists of a Ta/HfO2/RuO2 memristor operating in analog or digital modes, controlled by the reset voltage. The digital mode shows low dispersion and a high resistance ratio, and the analog mode enables precise conductance tuning. The local outlier factor is introduced to handle a heterogeneous density, and the required Euclidean and K-distances within the given dataset are calculated in the analog mode in parallel. In the digital mode, clustering is performed based on the connectivity among data points after excluding the detected outliers. The proposed algorithm boasts linear time complexity for the entire process. Extensive evaluations of synthetic datasets demonstrate significant improvement over representative density-based algorithms, and the datasets with heterogeneous density are clustered feasibly. Finally, the proposed algorithm is used to cluster the single-molecule localization microscopy data, demonstrating the feasibility of the suggested method for real-world problems.

A Genetic Algorithm Accelerator Based on Memristive Crossbar Array for Massively Parallel Computation

A Genetic Algorithm Accelerator Based on Memristive Crossbar Array for Massively Parallel Computation

Hyperplane tree-based data mining with a multi-functional memristive crossbar array.

This study explores the stochastic and binary switching behaviors of a Ta/HfO2/RuO2 memristor to implement a combined data mining approach for outlier detection and data clustering algorithms in a multi-functional memristive crossbar array. The memristor switches stochastically with high state dispersion in the stochastic mode and deterministically between two states with low dispersion in the binary mode, while they can be controlled by varying operating voltages. The stochastic mode facilitates the parallel generation of random hyperplanes in a tree structure, used to compress spatial information of the dataset in the Euclidian space into binary format, still retaining sufficient spatial features. The ensemble effect from multiple trees improved the classification performance. The binary mode facilitates parallel Hamming distance calculation of the binary codes containing spatial information, which measures similarity. These two modes enable efficient implementation of the newly proposed minority-based outlier detection method and modified K-means method on the same hardware. Array measurements and hardware simulations investigate various hyperparameters' impact and validate the proposed methods with practical datasets. The proposed methods show linear O(n) time complexity and high energy efficiency, consuming <1% of the energy compared to digital computing with conventional algorithms while demonstrating software-comparable performance in both tasks.

High‐Performance Memristors Based on Few‐Layer Manganese Phosphorus Trisulfide for Neuromorphic Computing

AbstractWhile transition‐metal thiophosphate (MPX3) materials have been a subject of extensive research in recent years, experimental studies on MPX3‐based memristors are still in their early stages, with device performance being less than ideal. Here, the successful fabrication of high‐yield, high‐performance, and uniform memristors are demonstrated to possess desired characteristics for neuromorphic computing using a single‐crystalline few‐layered manganese phosphorus trisulfide (MnPS3) as a resistive switching medium. The Ti/MnPS3/Au memristor exhibits small switching voltage (&lt;1 V), long memory retention (104 s), fast switching speed (≈20 ns), high On/Off ratio (nearly two orders of magnitude), and simultaneously achieves emulation of synaptic weight plasticity. The microscopic investigation of the structural and chemical characteristics of the few‐layer MnPS3 reveals the presence of structural defects and residual Ti throughout the stacked layer following the application of voltage, which contributes to the uniformity of switching with a low set voltage. With highly linear and symmetric analog weight updates coupled with the capability of accurate decimal arithmetic operations, a high accuracy of 95.15% in supervised learning using the MNIST handwritten recognition dataset is achieved in the artificial neural network. Furthermore, convolutional image processing can be implemented using hardware multiply‐and‐accumulate operation in an experimental memristor crossbar array.

Parallel Density‐Based Spatial Clustering with Dual‐Functional Memristive Crossbar Array

AbstractAnalog and digital switching performances in a Ta/HfO2/RuO2 (THR) memristor are studied to implement a density‐based spatial clustering of applications with noise (DBSCAN) algorithm in a low‐power, parallel‐computing memristor crossbar structure. In the analog mode THR memristor, more than 256 states can be stored through a fine‐tuning process with a denoising scheme. The analog mode crossbar array facilitates Euclidean distance calculation between any points in the given graphic dataset. In the digital mode, the on/off ratio of more than three orders of magnitude between the binary states is achieved, providing functionality to cluster the data points with a reduced number of operations. The parallel computing capacity of the adopted crossbar decreases the time complexity of the original DBSCAN from O(n2) to O(n). Through array‐level simulations, the effectiveness of hardware functionality is validated using representative synthetic datasets and single‐cell RNA sequences datasets.

MWA-MNN: Multi-patch Wavelet Attention Memristive Neural Network for image restoration

Adverse weather conditions can severely reduce the image quality captured by outdoor imaging devices. However, most existing image restoration algorithms are designed for specific tasks, lack generalization capabilities, and are unable to balance spatial details with contextual feature. Moreover, outdoor images are typically captured using edge devices with limited computing resources, rendering it challenging to deploy image restoration algorithms on edge devices. To tackle these problems, we propose a memristive-based image restoration algorithm, named Multi-patch Wavelet Attention Memristive Neural Network (MWA-MNN). Multiple image restoration tasks can be achieved by implementing Convolutional Neural Network (CNN) based on memristor crossbar arrays, as well as specified memristive circuits. Our proposed network comprises three sub-networks with multi-patch design enabling each sub-network to focus on different scales, thereby preserving more spatial details while fusing rich contextual feature. We propose the Discrete Wavelet Attention Block (DWAB) and the Coordinate Channel Attention Block (CCAB) to extract rich contextual information and the Supervised Selective Kernel Block (SSKB) to effectively filter the extracted features. Our proposed memristor-based circuit implementation provides an effective solution for deploying image restoration algorithms on edge devices. Experiment results on multiple benchmark datasets for image deraining, dehazing, and low-light image enhancement show that our proposed method outperforms over 20 state-of-the-art methods.

Research on the Impact of Data Density on Memristor Crossbar Architectures in Neuromorphic Pattern Recognition.

Binary memristor crossbars have great potential for use in brain-inspired neuromorphic computing. The complementary crossbar array has been proposed to perform the Exclusive-NOR function for neuromorphic pattern recognition. The single crossbar obtained by shortening the Exclusive-NOR function has more advantages in terms of power consumption, area occupancy, and fault tolerance. In this paper, we present the impact of data density on the single memristor crossbar architecture for neuromorphic image recognition. The impact of data density on the single memristor architecture is mathematically derived from the reduced formula of the Exclusive-NOR function, and then verified via circuit simulation. The complementary and single crossbar architectures are tested by using ten 32 × 32 images with different data densities of 0.25, 0.5, and 0.75. The simulation results showed that the data density of images has a negative effect on the single memristor crossbar architecture while not affecting the complementary memristor crossbar architecture. The maximum output column current produced by the single memristor crossbar array decreases as data density decreases while the complementary memristor crossbar array architecture provides stable maximum output column currents. When recognizing images with data density as low as 0.25, the maximum output column currents of the single memristor crossbar architecture is reduced four-fold compared with the maximum currents from the complementary memristor crossbar architecture. This reduction causes the Winner-take-all circuit to work incorrectly and will reduce the recognition rate of the single memristor crossbar architecture. These simulation results show that the single memristor crossbar architecture has more advantages compared with the complementary crossbar architecture when the images do have not many different densities, and none of the images have very low densities. This work also indicates that the single crossbar architecture must be improved by adding a constant term to deal with images that have low data densities. These are valuable case studies for archiving the advantages of single memristor crossbar architecture in neuromorphic computing applications.

A Design Methodology for Fault-Tolerant Neuromorphic Computing Using Bayesian Neural Network.

Memristor crossbar arrays are a promising platform for neuromorphic computing. In practical scenarios, the synapse weights represented by the memristors for the underlying system are subject to process variations, in which the programmed weight when read out for inference is no longer deterministic but a stochastic distribution. It is therefore highly desired to learn the weight distribution accounting for process variations, to ensure the same inference performance in memristor crossbar arrays as the design value. In this paper, we introduce a design methodology for fault-tolerant neuromorphic computing using a Bayesian neural network, which combines the variational Bayesian inference technique with a fault-aware variational posterior distribution. The proposed framework based on Bayesian inference incorporates the impacts of memristor deviations into algorithmic training, where the weight distributions of neural networks are optimized to accommodate uncertainties and minimize inference degradation. The experimental results confirm the capability of the proposed methodology to tolerate both process variations and noise, while achieving more robust computing in memristor crossbar arrays.

Efficient combinatorial optimization by quantum-inspired parallel annealing in analogue memristor crossbar

Combinatorial optimization problems are prevalent in various fields, but obtaining exact solutions remains challenging due to the combinatorial explosion with increasing problem size. Special-purpose hardware such as Ising machines, particularly memristor-based analog Ising machines, have emerged as promising solutions. However, existing simulate-annealing-based implementations have not fully exploited the inherent parallelism and analog storage/processing features of memristor crossbar arrays. This work proposes a quantum-inspired parallel annealing method that enables full parallelism and improves solution quality, resulting in significant speed and energy improvement when implemented in analog memristor crossbars. We experimentally solved tasks, including unweighted and weighted Max-Cut and traveling salesman problem, using our integrated memristor chip. The quantum-inspired parallel annealing method implemented in memristor-based hardware has demonstrated significant improvements in time- and energy-efficiency compared to previously reported simulated annealing and Ising machine implemented on other technologies. This is because our approach effectively exploits the natural parallelism, analog conductance states, and all-to-all connection provided by memristor technology, promising its potential for solving complex optimization problems with greater efficiency.

Edge learning using a fully integrated neuro-inspired memristor chip.

Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.