One-transistor (1T) memory devices with MFMPIS (Metal, Ferroelectrics, Metal, Polysilicon, Insulator, Semiconductor) and MFMIS (Metal, Ferroelectrics, Metal, Insulator, Semiconductor) structures have been widely studied. These memory devices exhibit very good switching property but very poor retention properties. Three possible mechanisms are responsible for the poor retention of 1T ferroelectric memories: namely, leakage current with charges trapping within the ferroelectric film, floating gate effect, and the depolarization field. The gate stack of ferroelectric memory transistor consists of a top electrode, a ferroelectric layer, a bottom electrode, and a gate insulator. The bottom electrode is a floating electrode acting as a floating gate. As long as there is field across the ferroelectric thin film there is leakage current. The leakage current charge up the floating gate, the charge accumulation at the floating gate neutralizes the polarization charge at the ferroelectric material and causes the device to loss memory property. In order to overcome this problem we fabricated a metal/ferroelectric on semiconductive metal oxide on silicon substrate structure. There is no insulator in the gate stack. These device structures do not have floating gate and the very low de-polarization field. Therefore, the memory retention time can be very long. In this paper, we will report the integration processes and the working MFMoxS device properties with improved retention properties.