Memory Management Scheme Research Articles

Grex: An efficient MapReduce framework for graphics processing units

In this paper, we present a new MapReduce framework, called Grex, designed to leverage general purpose graphics processing units (GPUs) for parallel data processing. Grex provides several new features. First, it supports a parallel split method to tokenize input data of variable sizes, such as words in e-books or URLs in web documents, in parallel using GPU threads. Second, Grex evenly distributes data to map/reduce tasks to avoid data partitioning skews. In addition, Grex provides a new memory management scheme to enhance the performance by exploiting the GPU memory hierarchy. Notably, all these capabilities are supported via careful system design without requiring any locks or atomic operations for thread synchronization. The experimental results show that our system is up to 12.4× and 4.1× faster than two state-of-the-art GPU-based MapReduce frameworks for the tested applications.

Power Failure Protection Scheme for Reliable High-Performance Solid State Disks

SUMMARY Solid-state disks (SSDs) have received much attention as replacements for hard disk drives (HDDs). One of their noticeable advantages is their high-speed read/write operation. To achieve good performance, SSDs have an internal memory hierarchy which includes several volatile memories, such as DRAMs and SRAMs. Furthermore, many SSDs adopt aggressive memory management schemes under the assumption of stable power supply. Unfortunately, the data stored in the volatile memories are lost when the power supplied to SSDs is abruptly shut off .S uch power failure is often observed in portable devices. For this reason, it is critical to provide a power failure protection scheme for reliable SSDs. In this work, we propose a power-failure protection scheme for SSDs to increase their reliability. The contribution of our work is three-fold. First, we design a power failure protection circuit which incorporates super-capacitors as well as rechargeable batteries. Second, we provide a method to determine the capacity of backup power sources. Third, we propose a data backup procedure when the power failure occurs. We implemented our method on a real board and applied it to a notebook PC with a contemporary SSD. The board measurement and simulation results prove that our method is robust

The next generation GPS memory management

The next generation Global Positioning System (GPS) will have many new features. Also the infrastructure will be noticeably enhanced. This has directed us to consider a new dynamic memory management strategy for the next generation GPS. The distinctiveness of the suggested infrastructure is shifting elements of the GPS applications to the operating system with the objective of managing application data more efficiently. A key component of any GPS application is caching its data with the intention of preventing excessive memory accesses and allocations. The suggested infrastructure called ‘Cache Based Dynamic Memory Management’ – CBDMM – aims at moving the caching component from the GPS application to the embedded operating system of the GPS. The paper introduces CBDMM design, discusses its advantages and shows several encouraging benchmarking results.

A comparison of GPU strategies for unstructured mesh physics

SUMMARYThere have been few efforts to date to write physics algorithms for general unstructured meshes (meshes composed of arbitrary polygons/polyhedra) on graphics processing units (GPUs). Typical strategies for GPU memory management, such as double‐buffering and coalescing memory accesses, are difficult to apply to the irregular memory storage patterns of unstructured meshes. This paper presents results from an initial GPU version of a typical unstructured mesh kernel. Three different memory management strategies are described and implemented. Timing results for all three strategies are presented, in some cases showing speedups of over 20 times compared with the original CPU code.Copyright © 2012 John Wiley & Sons, Ltd.

개인용 SSD를 위한 선반입 및 메모리 관리 정책

기존의 운영체제에서 하드디스크의 성능을 향상시키기 위해서 사용해왔던 기술들이 SSD(Solid State Drive)에는 부정적 효과를 나타내는 경우가 많다. HDD의 기계적인 요소 때문에 접근 시간과 블록 주소의 순서가 성능에 매우 중요한 요인으로 작용하였지만, SSD는 불록 주소의 순서에 영향을 받지 않는 우수한 랜덤 읽기 성능을 제공한다. 실제 개인용 PC에서 SSD를 사용할 때에 선반입을 끄도록 권고되고 있다. 하지만 이 논문은 SSD의 내부 구조와 낸드 플래시 메모리의 특징을 고려한 선반입 및 메모리관리 정책를 결합한 방법을 제시한다. SSD에는 다수개의 낸드 플래시 메모리로 구성되어 있어 칩을 동시에 구동시키는 것이 중요하며, 낸드 플래시 메모리의 기본 입출력 단위가 계속 증가하는 방향으로 발전하고 있어서 SSD 내부의 동작 단위가 운영체제의 블록 크기보다 훨씬 커지게 되었다. 이 논문은 이러한 SSD의 특징과 경향을 수용하여, 제안하는 선반입 기법은 SSD의 동작 단위로 수행되며, 제안하는 메모리 관리 기법은 그 선반입 기법의 단점을 보완하여, 캐시 히트율과 선반입 히트율의 합이 최대가 되도록, 선반입되었지만 사용되지 않는 데이터를 적응적으로 퇴출한다. 본 기술은 리눅스 커널 모듈로 개발하였으며 실제 SSD를 사용하여 성능 평가를 실시하였다. 주어진 실험에서 제안하는 선반입 기법이 약 26%까지 성능을 향상시켰다. Traditional technologies that are used to improve the performance of hard disk drives show many negative cases if they are applied to solid state drives (SSD). Access time and block sequence in hard disk drives that consist of mechanical components are very important performance factors. Meanwhile, SSD provides superior random read performance that is not affected by block address sequence due to the characteristics of flash memory. Practically, it is recommended to disable prefetching if a SSD is installed in a personal computer. However, this paper presents a combinational method of a prefetching scheme and a memory management that consider the internal structure of SSD and the characteristics of NAND flash memory. It is important that SSD must concurrently operate multiple flash memory chips. The I/O unit size of NAND flash memory tends to increase and it exceeded the block size of operating systems. Hence, the proposed prefetching scheme performs in an operating unit of SSD. To complement a weak point of the prefetching scheme, the proposed memory management scheme adaptively evicts uselessly prefetched data to maximize the sum of cache hit rate and prefetch hit rate. We implemented the proposed schemes as a Linux kernel module and evaluated them using a commercial SSD. The schemes improved the I/O performance up to 26% in a given experiment.

Power efficient motion estimation algorithm and architecture based on pixel truncation

A new block matching algorithm and its VLSI architecture for performing Motion Estimation (ME) are presented in this paper. In the reported fast two stage search algorithm, ME is performed in two stages. In the first stage, pixel truncation is used. In the second stage, ME is performed with full pixel resolution with an adaptive search pattern. The main advantage of the proposed algorithm is the inclusion of an early termination mechanism to reduce overall power consumption for the resulting architecture. The paper also introduces a suitable architecture to implement the proposed ME algorithm. In this architecture, a new memory management scheme has been proposed so that different bit planes can be accessed at different stages of ME from the same memory module. It has been shown that the proposed architecture can save approximately 27% power compared to another recently reported architecture. The proposed architecture can therefore be considered suitable for portable, battery-powered video consumer devices <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

An efficient hardware design for HDTV H.264/AVC encoder

This paper presents a hardware efficient high definition television (HDTV) encoder for H.264/AVC. We use a two-level mode decision (MD) mechanism to reduce the complexity and maintain the performance, and design a sharable architecture for normal mode fractional motion estimation (NFME), special mode fractional motion estimation (SFME), and luma motion compensation (LMC), to decrease the hardware cost. Based on these technologies, we adopt a four-stage macro-block pipeline scheme using an efficient memory management strategy for the system, which greatly reduces on-chip memory and bandwidth requirements. The proposed encoder uses about 1126k gates with an average Bjontegaard-Delta peak signal-to-noise ratio (BD-PSNR) decrease of 0.5 dB, compared with JM15.0. It can fully satisfy the real-time video encoding for 1080p@30 frames/s of H.264/AVC high profile.

CPU scheduling and memory management for interactive real-time applications

In this paper, we propose, design, implement, and evaluate a CPU scheduler and a memory management scheme for interactive soft real-time applications. Our CPU scheduler provides a new CPU reservati...

OpenGL ES 1.1 implementation based on OpenGL

In this paper, we present an efficient way of implementing OpenGL ES 1.1 3D graphics API library for the environments with hardware-supported OpenGL facility, typically as desktop PCs. Although OpenGL ES was started from the existing OpenGL features, it rapidly became the standard 3D graphics library customized for embedded systems through introducing fixed-point arithmetic operations, buffer management with fixed-point data type supports, completely new texture mapping functions and others. Currently, it is the official 3D graphics API for Google Android, Apple iPhone, Sony PlayStation3, etc. In this paper, we achieved improvements on the arithmetic operations for the fixed-point number representation, which is the most characteristic data type for OpenGL ES 1.1. For the conversion of fixed-point data types to the floating-point number representations for the underlying OpenGL, we show the way of efficient conversion processes even with satisfying OpenGL ES standard requirements. We also introduced a specialized memory management scheme to manage the converted data from the buffer containing fixed-point numbers. In the case of texture processing, the requirements in both standards are quite different, and thus we used completely new software-implementations. Our final implementation of OpenGL ES library provides all of more than 200 functions in the standard specification and passed its conformance test, to show its compliance with the standard. From the efficiency point of view, we measured its execution times for several OpenGL ES-specific application programs and achieved remarkable improvements.

Dynamic and adaptive SPM management for a multi-task environment

In this paper, we present a dynamic and adaptive scratchpad memory (SPM) management strategy targeting a multi-task environment. It can be applied to a contemporary embedded processor that maps the physically addressed SPM into a virtual space with the help of an integrated memory management unit (MMU). Based on mass-count disparity, we introduce a hardware memory reference sampling unit (MRSU) that samples the memory reference stream with very low probability. The captured address is considered as one of the memory addresses contained in a frequently referenced memory block. A hardware interruption is generated by the MRSU, and the identified frequently accessed memory block is placed into the SPM space by software. The software also modifies the page table so that the follow-up memory accesses to the memory block will be redirected to the SPM. With no dependence on compiler and profiling information, our proposed strategy is specifically adequate for SPM management in a multi-task environment. In such an environment, a real-time operating system (RTOS) is usually hosted, and the behavior of the memory accesses cannot be predicted by static analysis or profiling. We evaluate our SPM allocation strategy by running several tasks on a tiny RTOS with preemptive scheduling. Experimental results show that our approach can achieve 10% reduction in energy consumption on average, with 1% performance degradation at runtime compared with a cache-only reference system.

Design and implementation of embedded computer vision systems based on particle filters

Particle filtering methods are gradually attaining significant importance in a variety of embedded computer vision applications. For example, in smart camera systems, object tracking is a very important application and particle filter based tracking algorithms have shown promising results with robust tracking performance. However, most particle filters involve vast amount of computational complexity, thereby intensifying the challenges faced in their real-time, embedded implementation. Many of these applications share common characteristics, and the same system design can be reused by identifying and varying key system parameters and varying them appropriately. In this paper, we present a System-on-Chip (SoC) architecture involving both hardware and software components for a class of particle filters. The framework uses parameterization to enable fast and efficient reuse of the architecture with minimal re-design effort for a wide range of particle filtering applications as well as implementation platforms.Using this framework, we explore different design options for implementing three different particle filtering applications on field-programmable gate arrays (FPGAs). The first two applications involve particle filters with one-dimensional state transition models, and are used to demonstrate the key features of the framework. The main focus of this paper is on design methodology for hardware/software implementation of multi-dimensional particle filter application and we explore this in the third application which is a 3D facial pose tracking system for videos. In this multi-dimensional particle filtering application, we extend our proposed architecture with models for hardware/software co-design so that limited hardware resources can be utilized most effectively. Our experiments demonstrate that the framework is easy and intuitive to use, while providing for efficient design and implementation. We present different memory management schemes along with results on trade-offs between area (FPGA resource requirement) and execution speed.

An efficient clustering method for fast rendering of time-varying volumetric medical data

Visualization and exploration of time-varying volumetric medical data help clinicians for better diagnosis and treatment. However, it is a challenge to render these data in an interactive manner because of their complexity and large size. We propose an efficient clustering method for fast compression and rendering of these large dynamic data. We divide the volumes into a set of blocks and use a BIRCH (Balanced Iterative Reducing and Clustering using Hierarchies) based algorithm to cluster them, which can usually find a high quality clustering with a single scan of the blocks. In addition, the granularity of clusters can be adaptively adjusted by dynamically configuring threshold values. In each cluster of blocks, a KeyBlock is generated to represent the cluster, and therefore the storage space of the volumes is reduced greatly. In addition, we assign a lifetime to every KeyBlock and implement a dynamic memory management scheme to further reduce the storage space. During the rendering, each KeyBlock is rendered as a KeyImage, which can be reused if the view transformation and transfer function are not changed. This reuse can help to increase the rendering speed significantly. Experimental results showed that the proposed method can achieve good performance in terms of both speed optimization and space reduction.

High-performance operating system controlled online memory compression

Online memory compression is a technology that increases the amount of memory available to applications by dynamically compressing and decompressing their working datasets on demand. It has proven extremely useful in embedded systems with tight physical RAM constraints. The technology can be used to increase functionality, reduce size, and reduce cost, without modifying applications or hardware. This article presents a new software-based online memory compression algorithm for embedded systems. In comparison with the best algorithms used in online memory compression, our new algorithm has a competitive compression ratio but is twice as fast. In addition, we describe several practical problems encountered in developing an online memory compression infrastructure and present solutions. We present a method of adaptively managing the uncompressed and compressed memory regions during application execution. This memory management scheme adapts to the predicted memory requirements of applications. It permits efficient compression for a wide range of applications. We have evaluated our techniques on a portable embedded device and have found that the memory available to applications can be increased by 2.5× with negligible performance and power consumption penalties, and with no changes to hardware or applications. Our techniques allow existing applications to execute with less physical memory. They also allow applications with larger working datasets to execute on unchanged embedded system hardware, thereby increasing functionality.

Environment identification-based memory scheme for estimation of distribution algorithms in dynamic environments

In estimation of distribution algorithms (EDAs), the joint probability distribution of high-performance solutions is presented by a probability model. This means that the priority search areas of the solution space are characterized by the probability model. From this point of view, an environment identification-based memory management scheme (EI-MMS) is proposed to adapt binary-coded EDAs to solve dynamic optimization problems (DOPs). Within this scheme, the probability models that characterize the search space of the changing environment are stored and retrieved to adapt EDAs according to environmental changes. A diversity loss correction scheme and a boundary correction scheme are combined to counteract the diversity loss during the static evolutionary process of each environment. Experimental results show the validity of the EI-MMS and indicate that the EI-MMS can be applied to any binary-coded EDAs. In comparison with three state-of-the-art algorithms, the univariate marginal distribution algorithm (UMDA) using the EI-MMS performs better when solving three decomposable DOPs. In order to understand the EI-MMS more deeply, the sensitivity analysis of parameters is also carried out in this paper.

PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

A Software-Only Solution to Use Scratch Pads for Stack Data

A dynamic scratch pad memory (SPM) management scheme for program stack data with the objective of processor power reduction is presented. Basic technique does not need the SPM size at compile time, does not mandate any hardware changes, does not need profile information, and seamlessly integrates support for recursive functions. Stack frames are managed using a software SPM manager, integrated into the application binary, and shows average energy savings of 32% along with a performance improvement of 13%, on benchmarks from MiBench. SPM management can be further optimized and made pointer safe, by knowing the SPM size.

Access pattern based stream buffer management scheme for portable media players

Limited amount of main memories are often available on mobile phones and portable media players. In multitasking environments, however, programs often need to wait for pages to be loaded to the main memory, even for the pages once loaded but swapped out due to memory shortage. Such page fault mechanism provided by the operating system often becomes the main hindrance to the uninterrupted playback of multimedia players on portable electronic devices. In this paper, we propose a memory management scheme that helps multimedia players perform with a consistent quality, when other processes are concurrently running on memory limited environments. We devise a profile-based memory allocation scheme for multimedia stream buffers with the adoption of page prefetching and pinning. Using periodic monitoring points of main loops, we profile access patterns of memory, analyze the meaningful access patterns for stream buffers and provide the access pattern information for custom memory management. Our scheme helped reduce the number of page faults in heap. Reductions in page faults for a multimedia player are 60~80% under various memory-limited execution environments.

Dynamic memory balancing for virtual machines

Virtualization essentially enables multiple operating systems and applications to run on one physical computer by multiplexing hardware resources. A key motivation for applying virtualization is to improve hardware resource utilization while maintaining reasonable quality of service. However, such a goal cannot be achieved without efficient resource management. Though most physical resources, such as processor cores and I/O devices, are shared among virtual machines using time slicing and can be scheduled flexibly based on priority, allocating an appropriate amount of main memory to virtual machines is more challenging. Different applications have different memory requirements. Even a single application shows varied working set sizes during its execution. An optimal memory management strategy under a virtualized environment thus needs to dynamically adjust memory allocation for each virtual machine, which further requires a prediction model that forecasts its host physical memory needs on the fly. This paper introduces MEmory Balancer (MEB) which dynamically monitors the memory usage of each virtual machine, accurately predicts its memory needs, and periodically reallocates host memory. MEB uses two effective memory predictors which, respectively, estimate the amount of memory available for reclaiming without a notable performance drop, and additional memory required for reducing the virtual machine paging penalty. Our experimental results show that our prediction schemes yield high accuracy and low overhead. Furthermore, the overall system throughput can be significantly improved with MEB.

OpenGL을 이용한 OpenGL ES 1.1 구현

본 논문에서는 데스크탑과 같이 OpenGL 기능이 전용 하드웨어로 제공되는 환경을 대상으로, OpenGL ES 1.1 표준을 효율적으로 구현하는 방법을 제시한다. OpenGL ES는 기존의 OpenGL 표준을 바탕으로 하였지만, 고정소수점 연산, 이를 수용하는 버퍼 기능, 완전히 새로운 텍스처 처리 등의 도입으로, 임베디드 시스템에 특화된 3차원 그래픽스 라이브러리로 새롭게 제정되어, 구글 안드로이드, 애플 아이폰, 플레이스테이션3 등에서 공식 3차원 그래픽스 API로 채택되었다. 본 논문에서는 OpenGL ES의 특징적 자료형인 고정소수점 표현에 대한 산술 연산들을 개선하였고, 특히 고정소수점 자료형들을 부동소수점 형태로 변환하여 하위의 OpenGL API로 넘기는 과정에서 표준을 준수하면서도 효율적인 처리가 가능하도록 하였다. 새로 도입된 고정소수점 자료형을 허용하는 버퍼 기능에 대해서는 변환된 자료들을 별도의 메모리 공간에서 관리하는 방식으로 속도 향상에 중점을 두었으며, 요구 사항이 완전히 달라진 텍스처 처리 부분은 전체 기능을 별도의 소프트웨어로 완전히 새롭게 구현하였다. 최종 구현 결과인 OpenGL ES 라이브러리는 OpenGL ES 1.1 표준에 규정된 총 200여 함수를 제공하며, 표준인증 테스트를 완전히 통과하여 1.1 표준을 완벽히 만족시켰음을 보였다. 수행 속도 면에서는 OpenGL ES에 특화된 응용 프로그램들에 대한 처리 속도 측정에서 기존의 구현 사례들에 비해 최대 33.147배의 속도 향상을 가져왔으며, 동일한 범주의 구현 사례들 중에서 가장 빠른 구현 결과이다. In this paper, we present an efficient way of implementing OpenGL ES 1.1 standard for the environments with hardware-supported OpenGL API, such as desktop PCs. Although OpenGL ES was started from the existing OpenGL features, it becomes a new three-dimensional graphics library customized for embedded systems through introducing fixed-point arithmetic operations, buffer management with fixed-point data type supports, completely new texture mapping functionalities and others. Currently, it is the official three dimensional graphics library for Google Android, Apple iPhone, PlayStation3, etc. In this paper, we achieved improvements on the arithmetic operations for the fixed-point number representation, which is the most characteristic data type for OpenGL ES. For the conversion of fixed-point data types to the floating-point number representations for the underlying OpenGL, we show the way of efficient conversion processes even with satisfying OpenGL ES standard requirements. We also introduced a simple memory management scheme to mange the converted data for the buffer containing fixed-point numbers. In the case of texture processing, the requirements in both standards are quite different and thus we used completely new software-implementations. Our final implementation result of OpenGL ES library provides all of over than 200 functions in OpenGL ES 1.1 standard and completely passed its conformance test, to show its compliance with the standard. From the efficiency viewpoint, we measured its execution times for several OpenGL ES-specific application programs and achieved at most 33.147 times improvements, to become the fastest one among the OpenGL ES implementations in the same category.

Data-driven memory management for stream join

Memory management is a critical issue in stream processing involving stateful operators such as join. Traditionally, the memory requirement for a stream join is query-driven: a query has to explicitly define a window for each (potentially unbounded) input. The window essentially bounds the size of the buffer allocated for that stream. However, output produced this way may not be desirable (if the window size is not part of the intended query semantic) due to the volatile input characteristics. We discover that when streams are ordered or partially ordered, it is possible to use a data-driven memory management scheme to improve the performance. In this work, we present a novel data-driven memory management scheme, called Window-Oblivious Join (WO-Join), which adaptively adjusts the state buffer size according to the input characteristics. Our performance study shows that, compared to traditional Window-Join (W-Join), WO-Join is more robust with respect to the dynamic input and therefore produces higher quality results with lower memory costs.