Memory Copy Research Articles

Alteraciones neuropsicológicas de un paciente con enfermedad de Parkinson y antecedentes de consumo de sustancias psicoactivas

El objetivo de esta investigación fue describir el desempeño cognoscitivo de un paciente de sexo masculino, de 51 años, con 9 años de evolución de Enfermedad de Parkinson (EP) y antecedentes de consumo de sustancias psicoactivas, para lo cual se utilizó un protocolo neuropsicológico encontrando en el test de trazados (TMT-A 24/24 y TMT-B 24/24), prueba de Denominación de Boston (58/60), F.A.S- COWAT (28), Curva de Memoria California (Ascendente), copia (34/36) y evocación (26/36) de la Figura Compleja de Rey Osterrieth, Torre de Londres, Stroop de Colores (C 16”, P 31”, C-P 57”). Adicionalmente se aplicaron subpruebas del Test de Inteligencia Wechsler para adultos (WAISIII) (Retención de dígitos 9, sucesión letras-núeros 10, aritméica 11, dígito-símbolo 10, figuras incompletas 6, diseño con cubos 10, semejanzas 9), el perfil cognoscitivo se encuentra dentro de los paráetros normales para los procesos de lenguaje, memoria, praxias, y habilidades viso-construccionales; se evidencian leves alteraciones en atención, memoria de trabajo y funciones ejecutivas. El consumo prolongado de sustancias psicoactivas es un posible factor de riesgo en el desarrollo temprano de la EP, pero con un perfil cognoscitivo conservado que se puede explicar por su nivel académico previo y su continuo ejercicio intelectual en su profesión, que le exigen constantes actividades cognitivas.

HiCOO: Hierarchical cooperation for scalable communication in Global Address Space programming models on Cray XT systems

Global Address Space (GAS) programming models enable a convenient, shared-memory style addressing model. Typically this is realized through one-sided operations that can enable asynchronous communication and data movement. With the size of petascale systems reaching 10,000s of nodes and 100,000s of cores, the underlying runtime systems face critical challenges in (1) scalably managing resources (such as memory for communication buffers), and (2) gracefully handling unpredictable communication patterns and any associated contention. For any solution that addresses these resource scalability challenges, equally important is the need to maintain the performance of GAS programming models. In this paper, we describe a Hierarchical COOperation (HiCOO) architecture for scalable communication in GAS programming models. HiCOO formulates a cooperative communication architecture: with inter-node cooperation amongst multiple nodes (a.k.a multinode) and hierarchical cooperation among multinodes that are arranged in various virtual topologies. We have implemented HiCOO for a popular GAS runtime library, Aggregate Remote Memory Copy Interface (ARMCI). By extensively evaluating different virtual topologies in HiCOO in terms of their impact to memory scalability, network contention, and application performance, we identify MFCG as the most suitable virtual topology. The resulting HiCOO architecture is able to realize scalable resource management and achieve resilience to network contention, while at the same time maintaining or enhancing the performance of scientific applications. In one case, it reduces the total execution time of an NWChem application by 52%.

An MPI-CUDA Implementation and Optimization for Parallel Sparse Equations and Least Squares (LSQR)

LSQR (Sparse Equations and Least Squares) is a widely used Krylov subspace method to solve large-scale linear systems in seismic tomography. This paper presents a parallel MPI-CUDA implementation for LSQR solver. On CUDA level, our contributions include: (1) utilize CUBLAS and CUSPARSE to compute major steps in LSQR; (2) optimize memory copy between host memory and device memory; (3) develop a CUDA kernel to perform transpose SpMV without transposing the matrix in memory or preserving additional copy. On MPI level, our contributions include: (1) decompose both matrix and vector to increase parallelism; (2) design a static load balancing strategy. In our experiment, the single GPU code achieves up to 17.6x speedup with 15.7 GFlops in single precision and 15.2x speedup with 12.0 GFlops in double precision compared with the original serial CPU code. The MPI-GPU code achieves up to 3.7x speedup with 268 GFlops in single precision and 3.8x speedup with 223 GFlops in double precision on 135 MPI tasks compared with the corresponding MPI-CPU code. The MPI-GPU code scales on both strong and weak scaling tests. In addition, our parallel implementations have better performance than the LSQR subroutine in PETSc library.

Performance characterization of global address space applications: a case study with NWChem

SUMMARYThe use of global address space languages and one‐sided communication for complex applications is gaining attention in the parallel computing community. However, lack of good evaluative methods to observe multiple levels of performance makes it difficult to isolate the cause of performance deficiencies and to understand the fundamental limitations of system and application design for future improvement. NWChem is a popular computational chemistry package, which depends on the Global Arrays/Aggregate Remote Memory Copy Interface suite for partitioned global address space functionality to deliver high‐end molecular modeling capabilities. A workload characterization methodology was developed to support NWChem performance engineering on large‐scale parallel platforms. The research involved both the integration of performance instrumentation and measurement in the NWChem software, as well as the analysis of one‐sided communication performance in the context of NWChem workloads. Scaling studies were conducted for NWChem on Blue Gene/P and on two large‐scale clusters using different generation Infiniband interconnects and x86 processors. The performance analysis and results show how subtle changes in the runtime parameters related to the communication subsystem could have significant impact on performance behavior. The tool has successfully identified several algorithmic bottlenecks, which are already being tackled by computational chemists to improve NWChem performance. Copyright © 2011 John Wiley & Sons, Ltd.

A CPU–GPU hybrid approach for the unsymmetric multifrontal method

Multifrontal is an efficient direct method for solving large-scale sparse and unsymmetric linear systems. The method transforms a large sparse matrix factorization process into a sequence of factorizations involving smaller dense frontal matrices. Some of these dense operations can be accelerated by using a graphic processing unit (GPU). We analyze the unsymmetric multifrontal method from both an algorithmic and implementational perspective to see how a GPU, in particular the NVIDIA Tesla C2070, can be used to accelerate the computations. Our main accelerating strategies include (i) performing BLAS on both CPU and GPU, (ii) improving the communication efficiency between the CPU and GPU by using page-locked memory, zero-copy memory, and asynchronous memory copy, and (iii) a modified algorithm that reuses the memory between different GPU tasks and sets thresholds to determine whether certain tasks be performed on the GPU. The proposed acceleration strategies are implemented by modifying UMFPACK, which is an unsymmetric multifrontal linear system solver. Numerical results show that the CPU–GPU hybrid approach can accelerate the unsymmetric multifrontal solver, especially for computationally expensive problems.

PARALLEL 3D FINITE-DIFFERENCE TIME-DOMAIN METHOD ON MULTI-GPU SYSTEMS

Finite-difference time-domain (FDTD) is a popular but computational intensive method to solve Maxwell's equations for electrical and optical devices simulation. This paper presents implementations of three-dimensional FDTD with convolutional perfect match layer (CPML) absorbing boundary conditions on graphics processing unit (GPU). Electromagnetic fields in Yee cells are calculated in parallel millions of threads arranged as a grid of blocks with compute unified device architecture (CUDA) programming model and considerable speedup factors are obtained versus sequential CPU code. We extend the parallel algorithm to multiple GPUs in order to solve electrically large structures. Asynchronous memory copy scheme is used in data exchange procedure to improve the computation efficiency. We successfully use this technique to simulate pointwise source radiation and validate the result by comparison to high precision computation, which shows favorable agreements. With four commodity GTX295 graphics cards on a single personal computer, more than 4000 million Yee cells can be updated in one second, which is hundreds of times faster than traditional CPU computation.

Cache-Based Memory Copy Hardware Accelerator for Multicore Systems

In this paper, we present a new architecture of the cache-based memory copy hardware accelerator in a multicore system supporting message passing. The accelerator is able to accelerate memory data movements, in particular memory copies. We perform an analytical analysis based on open-queuing theory to study the utilization of our accelerator in a multicore system. In order to correctly model the system, we gather the necessary information by utilizing a full-system simulator. We present both the simulation results and the analytical analysis. We demonstrate the advantages of our solution based on a full-system simulator utilizing several applications: the STREAM benchmark and the receiver-side of the TCP/IP stack. Our accelerator provides speedups from 2.96 to 4.61 for the receiver-side of the TCP/IP stack, reduces the number of instructions from 26 percent to 44 percent and achieves a higher cache hit rate. Utilizing the analytical analysis, our accelerator reduces in the average number of cycles executed per instruction up to 50 percent for one of the CPUs in the multicore system.

Redesigning the message logging model for high performance

AbstractOver the past decade the number of processors used in high performance computing has increased to hundreds of thousands. As a direct consequence, and while the computational power follows the trend, the mean time between failures (MTBF) has suffered and is now being counted in hours. In order to circumvent this limitation, a number of fault‐tolerant algorithms as well as execution environments have been developed using the message passing paradigm. Among them, message logging has been proved to achieve a better overall performance when the MTBF is low, mainly due to a faster failure recovery. However, message logging suffers from a high overhead when no failure occurs. Therefore, in this paper we discuss a refinement of the message logging model intended to improve the failure‐free message logging performance. The proposed approach simultaneously removes useless memory copies and reduces the number of logged events. We present the implementation of a pessimistic message logging protocol in Open MPI and compare it with the previous reference implementation MPICH‐V2. The results outline a several order of magnitude improvement on the performance and a zero overhead for most messages. Published in 2010 by John Wiley & Sons, Ltd.

Cooperative server clustering for a scalable GAS model on petascale cray XT5 systems

Global Address Space (GAS) programming models are attractive because they retain the easy-to-use addressing model that is the characteristic of shared-memory style load and store operations. The scalability of GAS models depends directly on the design and implementation of runtime libraries on the targeted platforms. In this paper, we examine the memory requirement of a popular GAS run-time library, Aggregate Remote Memory Copy Interface (ARMCI) on petascale Cray XT 5 systems. Then we describe a new technique cooperative server clustering that enhances the memory scalability of ARMCI communication servers. In cooperative server clustering, ARMCI servers are organized into clusters, and cooperatively process incoming communication requests among them. A request intervention scheme is also designed to expedite the return of responses to the initiating processes. Our experimental results demonstrate that, with very little impact on ARMCI communication latency and bandwidth, cooperative server clustering is able to significantly reduce the memory requirement of ARMCI communication servers, thereby enabling highly scalable scientific applications. In particular, it dramatically reduces the total execution time of a scientific application, NWChem, by 45% on 2400 processes.

Evaluation of a just-in-time compiler retrofitted for PHP

Programmers who develop Web applications often use dynamic scripting languages such as Perl, PHP, Python, and Ruby. For general purpose scripting language usage, interpreter-based implementations are efficient and popular but the server-side usage for Web application development implies an opportunity to significantly enhance Web server throughput. This paper summarizes a study of the optimization of PHP script processing. We developed a PHP processor, P9, by adapting an existing production-quality just-in-time (JIT) compiler for a Java virtual machine, for which optimization technologies have been well-established, especially for server-side application. This paper describes and contrasts microbenchmarks and SPECweb2005 benchmark results for a well-tuned configuration of a traditional PHP interpreter and our JIT compiler-based implementation, P9. Experimental results with the microbenchmarks show 2.5-9.5x advantage with P9, and the SPECweb2005 measurements show about 20-30% improvements. These results show that the acceleration of dynamic scripting language processing does matter in a realistic Web application server environment. CPU usage profiling shows our simple JIT compiler introduction reduces the PHP core runtime overhead from 45% to 13% for a SPECweb2005 scenario, implying that further improvements of dynamic compilers would provide little additional return unless other major overheads such as heavy memory copy between the language runtime and Web server frontend are reduced.

Full user data acquisition from Symbian smart phones

Currently there is a lack of non-intrusive methods to create linear bitwise copies of the internal flash memory of Symbian smart phones. Furthermore, little is known about the locations and the format in which Symbian OS stores data. The goal of this research is to create a software tool that can be executed on the Symbian OS and creates linear bitwise copies of the internal flash memory. The result is the Symbian Memory Imaging Tool (SMIT) which can image the volumes of the internal flash memory and copies the images to a removable memory device. The SMIT opens the way to retrieve deleted data in a non-intrusive manner. Additionally, a preliminary exploration of the Symbian user volume was performed to determine the locations of forensically important (deleted) data.

GAMER : A GRAPHIC PROCESSING UNIT ACCELERATED ADAPTIVE-MESH-REFINEMENT CODE FOR ASTROPHYSICS

We present the newly developed code, GAMER (GPU-accelerated Adaptive MEsh Refinement code), which has adopted a novel approach to improve the performance of adaptive mesh refinement (AMR) astrophysical simulations by a large factor with the use of the graphic processing unit (GPU). The AMR implementation is based on a hierarchy of grid patches with an oct-tree data structure. We adopt a three-dimensional relaxing TVD scheme for the hydrodynamic solver, and a multi-level relaxation scheme for the Poisson solver. Both solvers have been implemented in GPU, by which hundreds of patches can be advanced in parallel. The computational overhead associated with the data transfer between CPU and GPU is carefully reduced by utilizing the capability of asynchronous memory copies in GPU, and the computing time of the ghost-zone values for each patch is made to diminish by overlapping it with the GPU computations. We demonstrate the accuracy of the code by performing several standard test problems in astrophysics. GAMER is a parallel code that can be run in a multi-GPU cluster system. We measure the performance of the code by performing purely-baryonic cosmological simulations in different hardware implementations, in which detailed timing analyses provide comparison between the computations with and without GPU(s) acceleration. Maximum speed-up factors of 12.19 and 10.47 are demonstrated using 1 GPU with 4096^3 effective resolution and 16 GPUs with 8192^3 effective resolution, respectively.

Topographical disorientation in Alzheimer's disease

Topographical disorientation (TD) has not been as extensively studied as other frequent manifestations of Alzheimer's disease (AD). To verify the occurrence of TD and to identify the neuropsychological dysfunctions associated with TD in AD. Thirty patients with probable AD, their caregivers and 30 subjects without dementia (controls) were interviewed with a questionnaire and evaluated with tests related to topographical orientation. AD patients, even those with mild dementia, differ from controls in the questionnaire on topographical orientation and in most neuropsychological tests except for tests of spatial working memory, point localization, three dimension and nonsense figure copy. When the performances in the neuropsychological tests of patients with mild or moderate dementia were compared, only landmark recognition and route description were more impaired in moderate dementia. TD occurs even in mild dementia of AD, a finding apparently not explained by the impairments of more elementary spatial functions.

Design and implementation of a high‐performance CCA event service

AbstractEvent services based on publish–subscribe architectures are well‐established components of distributed computing applications. Recently, an event service has been proposed as part of the common component architecture (CCA) for high‐performance computing (HPC) applications. In this paper we describe our implementation, experimental evaluation, and initial experience with a high‐performance CCA event service that exploits efficient communications mechanisms commonly used on HPC platforms. We describe the CCA event service model and briefly discuss the possible implementation strategies of the model. We then present the design and implementation of the event service using the aggregate remote memory copy interface as an underlying communication layer for this mechanism. Two alternative implementations are presented and evaluated on a Cray XD‐1 platform. The performance results demonstrate that event delivery latencies are low and that the event service is able to achieve high‐throughput levels. Finally, we describe the use of the event service in an application for high‐speed processing of data from a mass spectrometer and conclude by discussing some possible extensions to the event service for other HPC applications. Published in 2009 by John Wiley & Sons, Ltd.

MESSAGE PASSING WITHOUT MEMORY COPY

We consider here reduction of send latencies for send-and-forget type communications, where senders do not reuse data that have already been sent. We introduce a commit based message sending approach, and describe the corresponding application programming interfaces. These interfaces allow applications to take advantage of message buffering, such as overlapping of computations and communications, while avoiding performance degradation due to intermediate memory copy. The approach works by allowing applications to safely access the implementation buffer through the provided interfaces. Experimental results show that the new approach is effective, and reduces the interface latency significantly compared to related approaches. Since send-and-forget type communications are often observed in skeletal programming, we demonstrate the approach by implementing a pipeline algorithmic skeleton.

Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs

In this paper, “Martini,” a network interface controller chip for our original network called RHiNET is described. Martini is designed to provide high-bandwidth and low-latency communication with small overhead. To obtain high performance communication, protected user-level zero-copy RDMA communication functions are completely implemented by a hardwired logic. Also, to reduce the communication latency efficiently, we have proposed PIO-based communication mechanisms called “On-the-fly (OTF)” and have implemented them on Martini. The evaluation results show that Martini connected to a 64bit/66MHz PCI-bus achieves 470MByte/s maximum bidirectional bandwidth and 1.74 μsec minimum latency on host-to-host memory copying.

Data Acquisition from Cell Phone using Logical Approach

Abstract — Cell phone forensics to acquire and analyze data in the cellular phone is nowadays being used in a national investigation organization and a private company. In order to collect cellular phone flash memory data, we have two methods. Firstly, it is a logical method which acquires files and direct ories from the file system of the cell phone flash memory. Secondly, we can get all data from bit-by-bit copy of entire physical memory using a low level access method. In this paper, we describe a forensic tool to acquire cell phone flash memory data using a logical level approach. By our tool, we can get EFS file system and peek memory data with an arbitrary region from Korea CDMA cell phone. Keywords — Forensics, logical method, acquisition, cell phone, flash memory.I. I NTRODUCTION S digital evidence that kept in the various electronic media such as a computer and a mobile device in the digital crime is recently increasing, digital forensic technology to prove the crime is being more and more important. Especially, if the critical evidence is stored in the mobile devices, mobile forensic technology is demanded to find out the evidence without damage of the evidence. Mobile devices include small scale digital devices, embedded system, portable storage devices, and obscure devices. And, as to the small scale digital devices, there are various types of cell phones, USIM, PDA, navigation system, game player, and so on. In this paper, we are focusing in acquiring and analyzing data in the cell phone. User data such as phonebook, call history, SMS, and photo and hardware-related data such as IMSI, MIN, and ESN are mainly stored in the NAND flash memory and the NOR flash memory of the cell phone. In case of Korea, most of

Cognition and functional outcome among deaf and hearing people with schizophrenia

Recent research has highlighted the relationships between impairments in cognitive functioning and poorer functional outcomes among people with schizophrenia (PWS). The purpose of this study was to replicate and extend this work by testing the relationships between cognition and functional outcome among deaf adults with schizophrenia. Empirical findings from deafness-oriented research reveals enhanced abilities in certain aspects of visual–spatial processing compared to hearing people. Sixty-five PWS (34 deaf, 31 hearing) were assessed using measures of verbal and visual memory, attention, and visual processing. The first hypothesis tested whether cognition predicted functional outcome in a similar fashion for both deaf and hearing subjects (n=63). For all subjects, higher levels of cognitive ability were associated with higher levels of functional outcome, and the strongest predictors of outcome were verbal memory and visual–spatial memory (recall condition) (VSM recall). However, the deaf and hearing groups did show different patterns of relationships between cognition and functioning when all cognitive variables were examined. The second hypothesis was that deaf subjects would display superior performance in early visual processing, visual–spatial memory (copy condition) (VSM copy), and VSM recall. Deaf subjects displayed superior performance on each task; however, no significant differences emerged. Deaf subjects outperformed hearing subjects in an unexpected domain (word memory/recognition). This study extends prior work in the area of cognition and schizophrenia and indicates that deaf and hearing subjects may benefit from interventions that address different domains of cognition.

The figure copy and recall test of the Adult Memory and Information Processing Battery: Inter‐rater reliability

Examined inter-rater reliability of the scoring of the Figure Copy and Recall subtest of the Adult Memory and Information Processing Battery (AMIPB; Coughlan & Hollows, 1985). Figure Copy and Recall tests of 56 individuals referred for neuropsychological assessment were independently scored by three experienced neuropsychologists and the scores correlated. Detailed analysis of reasons for scoring discrepancies was carried out. Raters scores were highly correlated in relation to both forms of the tests. The major source of discrepancy was errors in accuracy. Results indicate that the AMIPB manual instructions are sufficiently detailed to obtain good inter-rater reliability when the raters are experienced clinicians. Further research using trainees or assistant psychologists is suggested.

Hardware Support for Accelerating Data Movement in Server Platform

Data movement (memory copies) is a very common operation during network processing and application execution on servers. The performance of this operation is rather poor on today's microprocessors due to the following aspects: 1) Several long-latency memory accesses are involved because the source and/or the destination are typically in memory, 2) latency hiding techniques, such as out-of-order execution, hardware threading, and prefetching, are not very effective for bulk data movement, and 3) microprocessors move data at register (small) granularity. In this paper, we show this overhead of bulk data movement and propose the use of dedicated copy engines to minimize it. We present a detailed analysis of copy engine architectures along two dimensions: 1) on-die versus off-die and 2) synchronous versus asynchronous. These copy engine architectures are superior to traditional direct memory access (DMA) engines because they are tightly coupled to the core architecture and enable lower overhead communication and signaling. We describe the hardware support required to implement these copy engines and integrate them into server platforms. We perform a detailed case study to evaluate the performance of these copy engines. The evaluation is based on an execution-driven simulator, which was extended with detailed models of copy engines. Our simulation results show that copy engines are effective in reducing the bulk data movement overhead and, hence, hold significant promise for high-performance server platforms