Memory Copy Research Articles

Build a trusted storage system on a mobile phone

The authors introduce their design, implementation and formally verification of a Trusted Execution Environment (TEE)-based trusted storage system (TSS) in mobile devices, which conforms to GlobalPlatform specifications. The authors' TSS provides not only authenticating the integrity and freshness of data but also many security storage operation properties like atomicity operations of a persistent object. To improve data store efficient when a big persistent object is read or written, a new mechanism that dynamic allocate continuous memory in REE's kernel memory space and map the address to the TEE through a communication pipe is proposed. This method can reduce switching times, allocating memory times and copy memory overloads between two worlds. A formal method is used in their design and development to guarantee the correctness and security of TSS. They consider the functional correctness mainly in this study, and use traditional formal verification tool - VCC verify the functional correctness of TSS. Their evaluation demonstrates its advantage compared to existing systems in addition.

On the support of inter-node P2P GPU memory copies in rCUDA

Although GPUs are being widely adopted in order to noticeably reduce the execution time of many applications, their use presents several side effects such as an increased acquisition cost of the cluster nodes or an increased overall energy consumption. To address these concerns, GPU virtualization frameworks could be used. These frameworks allow accelerated applications to transparently use GPUs located in cluster nodes other than the one executing the program. Furthermore, these frameworks aim to offer the same API as the NVIDIA CUDA Runtime API does, although different frameworks provide different degree of support. In general, and because of the complexity of implementing an efficient mechanism, none of the existing frameworks provides support for memory copies between remote GPUs located in different nodes.In this paper we introduce an efficient mechanism devised for addressing the support for this kind of memory copies among GPUs located in different cluster nodes. Several options are explored and analyzed, such as the use of the GPUDirect RDMA mechanism. We focus our discussion on the rCUDA remote GPU virtualization framework. Results show that is possible to implement this kind of memory copies in such an efficient way that performance is even improved with respect to the original performance attained by CUDA when GPUs located in the same cluster node are leveraged.

Cycle Time Improvement of EtherCAT Networks with Embedded Linux-Based Master

We improve the cycle time performance of EtherCAT networks with embedded Linux-based master by developing a Linux Ethernet driver optimized for EtherCAT operation. The Ethernet driver is developed to establish a direct interface between the master module and Ethernet controllers of embedded systems by removing the involvement of Linux network stack and the New API (NAPI) of standard Ethernet drivers. Consequently, it is achieved that the time-consuming memory copy operations are reduced and the process of EtherCAT frames is accelerated. In order to demonstrate the effect of the developed Ethernet driver, we set up EtherCAT networks composed of an embedded Linux-based master and commercial off-the-shelf slaves, and the experimental results confirm that the cycle time performance is significantly improved.

Structural white matter networks in myotonic dystrophy type 1.

The myriad of neuropsychiatric manifestations reported in myotonic dystrophy type 1 may have its origin in alterations of complex brain network interactions at the structural level. In this study, we tested the hypothesis that altered white matter microstructural integrity and network organisation were present in a cohort of individuals with DM1 compared to unaffected controls, which was expected to be associated with CNS related disease manifestations of DM1. We performed a cross-sectional neuropsychological assessment and brain MRI in 25 myotonic dystrophy type 1 (DM1) patients and 26 age, sex and educational level matched unaffected controls. Patients were recruited from the Dutch cohort of the OPTIMISTIC study, a concluded trial which had included ambulant, genetically confirmed DM1 patients who were severely fatigued. We applied graph theoretical analysis on structural networks derived from diffusion tensor imaging (DTI) data and deterministic tractography to determine global and local network properties and performed group-wise comparisons. Furthermore, we analysed the following variables from structural MRI imaging: semi-quantitative white matter hyperintensity load andwhite matter tract integrity using tract-based spatial statistics (TBSS). Structural white matter networks in DM1 were characterised by reduced global efficiency, local efficiency and strength, while the network density was compatible to controls. Other findings included increased white matter hyperintensity load, and diffuse alterations of white matter microstructure in projection, association and commissural fibres. DTI and network measures were associated (partial correlations coefficients ranging from 0.46 to 0.55) with attention (d2 Test), motor skill (Purdue Pegboard test) and visual-constructional ability and memory (copy subtest of the Rey-Osterrieth Complex Figure Test). DTI and network measures were not associated with clinical measures of fatigue (checklist individual strength, fatigue subscale) or apathy (apathy evaluation scale – clinician version). In conclusion, our study supports the view of brain involvement in DM1 as a complex network disorder, characterised by white matter network alterations that may have relevant neuropsychological correlations. This work was supported by the European Community's Seventh Framework Programme (FP7/2007–2013; grant agreement n° 305,697) and the Marigold Foundation.

Bandwidth Provisioning for Virtual Machine Migration in Cloud: Strategy and Application

Physical resources are highly virtualized in today's datacenter-based cloud-computing networks. Servers, for example, are virtualized as Virtual Machines (VMs). Through abstraction of physical resources, server virtualization enables migration of VMs over the interconnecting network. VM migration can be used for load balancing, energy conservation, disaster protection, etc. Migration of a VM involves iterative memory copy and network re-configuration. Memory states are transferred in multiple phases to keep the VM alive during the migration process, with a small downtime for switchover. Significant network resources are consumed during this process. Migration also results in undesirable performance impacts. Suboptimal network bandwidth assignment, inaccurate pre-copy iterations, and high end-to-end network delay in wide-area networks (WAN) can exacerbate the performance degradation. In this study, we devise strategies to find suitable bandwidth and pre-copy iteration count to optimize different performance metrics of VM migration over a WAN. First, we formulate models to measure network resource consumption, migration duration, and migration downtime. Then, we propose a strategy to determine appropriate migration bandwidth and number of pre-copy iterations, and perform numerical experiments in multiple cloud environments with large number of migration requests. Results show that our approach consumes less network resources when compared with maximum and minimum-bandwidth provisioning strategies while using an order of magnitude less bandwidth than maximum-bandwidth strategy. It also achieves significantly lower migration duration than minimum-bandwidth scheme.

Vaex: big data exploration in the era of Gaia

We present a new Python library, called vaex, intended to handle extremely large tabular datasets such as astronomical catalogues like the Gaia catalogue, N-body simulations, or other datasets which can be structured in rows and columns. Fast computations of statistics on regular N-dimensional grids allows analysis and visualization in the order of a billion rows per second, for a high-end desktop computer. We use streaming algorithms, memory mapped files, and a zero memory copy policy to allow exploration of datasets larger than memory, for example out-of-core algorithms. Vaex allows arbitrary (mathematical) transformations using normal Python expressions and (a subset of) numpy functions which are “lazily” evaluated and computed when needed in small chunks, which avoids wasting of memory. Boolean expressions (which are also lazily evaluated) can be used to explore subsets of the data, which we call selections. Vaex uses a similar DataFrame API as Pandas, a very popular library, which helps migration from Pandas. Visualization is one of the key points of vaex, and is done using binned statistics in 1d (e.g. histogram), in 2d (e.g. 2d histograms with colourmapping) and 3d (using volume rendering). Vaex is split in in several packages: vaex-core for the computational part, vaex-viz for visualization mostly based on matplotlib, vaex-jupyter for visualization in the Jupyter notebook/lab based in IPyWidgets, vaex-server for the (optional) client-server communication, vaex-ui for the Qt based interface, vaex-hdf5 for HDF5 based memory mapped storage, vaex-astro for astronomy related selections, transformations, and memory mapped (column based) FITS storage.

GPU parallelization of sequence segmentation using information theoretic models

Sequence segmentation has gained popularity in bioinformatics and particularly in studying DNA sequences. Information theoretic models have been used in providing accurate solutions in the segmentation of DNA sequences. Existing dynamic programming approaches provide optimal solution to the segmentation problem. However, their quadratic time complexity prohibits their applicability to long sequences. In this paper, we propose a parallel approach to improve the performance of a quasilinear sequence segmentation algorithm. The target segmentation technique is a divide-and-conquer recursive algorithm that is based on information theory principles and models. We present three parallel implementations that aim at reducing the segmentation time. The first implementation uses the multithreading capabilities of CPUs. The second one is a hybrid implementation that utilizes the synergy between the CPU and the multithreading power of GPUs. The third implementation is a variation of the hybrid approach where it utilizes the concept of unified memory between the CPU and the GPU instead of the standard memory copy approach. We demonstrate the applicability of the parallel implementations by testing them on real DNA sequences and randomly generated sequences with different lengths and different number of unique elements. The results show that the hybrid CPU-GPU approach outperforms the sequential implementation with a speedup of up to 5.9X while the CPU parallel implementation provides a poor speedup of only 1.7X.

Automatic Hierarchical Parallelization of Linear Recurrences

Linear recurrences encompass many fundamental computations including prefix sums and digital filters. Later result values depend on earlier result values in recurrences, making it a challenge to compute them in parallel. We present a new work- and space-efficient algorithm to compute linear recurrences that is amenable to automatic parallelization and suitable for hierarchical massively-parallel architectures such as GPUs. We implemented our approach in a domain-specific code generator that emits optimized CUDA code. Our evaluation shows that, for standard prefix sums and single-stage IIR filters, the generated code reaches the throughput of memory copy for large inputs, which cannot be surpassed. On higher-order prefix sums, it performs nearly as well as the fastest handwritten code from the literature. On tuple-based prefix sums and digital filters, our automatically parallelized code outperforms the fastest prior implementations.

Cache-Oblivious MPI All-to-All Communications Based on Morton Order

Many-core systems with a rapidly increasing number of cores pose a significant challenge to parallel applications to use their complex memory hierarchies efficiently. Many such applications rely on collective communications in performance-critical phases, which become a bottleneck if they are not optimized. We address this issue by proposing cache-oblivious algorithms for MPI_Alltoall, MPI_Allgather, and the MPI neighborhood collectives to exploit the data locality. To implement the cache-oblivious algorithms, we allocate the send and receive buffers on a shared heap and use Morton order to guide the memory copies. Our analysis shows that our algorithm for MPI_Alltoall is asymptotically optimal. We show an extension to our algorithms to minimize the communication distance on NUMA systems while maintaining optimality within each socket. We further demonstrate how the cache-oblivious algorithms can be applied to multi-node machines. Experiments are conducted on different many-core architectures. For MPI_Alltoall, our implementation achieves on average 1.40X speedup over the naive implementation based on shared heap for small and medium block sizes (less than 16 KB) on a Xeon Phi KNC, achieves on average 3.03X speedup over MVAPICH2 on a Xeon E7-8890, and achieves on average 2.23X speedup over MVAPICH2 on a 256-node Xeon E5-2680 cluster for block sizes less than 1 KB.

Effects of subjective sleep status on the cognition of the elderly in community

Objective To explore the effects of sleep status on the cognition of the elderly in community, so as to provide evidence for the prevention and reduction of cognitive decline. Methods A total of 192 healthy elderly people from 2 communities in Haidian District of Beijing were selected by convenience sampling method. All the objects were investigated with Mini Mental State Examination (MMSE) , repeatable Battery for the Assessment of Neuropsychological Status (rBANS) , Activities of Daily Living (ADL) and Physical Activity Scale for the Elderly (PASE) after signing the consent form. The influencing factors of the cognition function were analyzed by multiple linear regression. Results Within the 192 healthy elderly, 42 individuals reported having subjective sleep problems, and 150 individuals reporting normal sleep. There was no significant difference in gener, age and education level between the two groups (P>0.05) . In rBANS assessment, the score of list learning of the sleep problem group (19.21±6.06) was lower than that of the normal sleep group (21.69±5.82) , with statistical significance (t=2.42, P=0.02) . However, there was no significant difference between two groups in the other 11 subtests of rBANS, such as story memory and figure copy (P>0.05) . In addition, there were no significant differences in the total score of MMSE, ADL and PASE between the two groups (P>0.05) . Multiple linear regression analysis showed that age, year of education, and sleep disorder had impacts on list learning (P<0.05) . Conclusions The subjective reporting of poor sleep has an adverse effect on the short-term verbal memory in elderly who are in a general healthy situation. Sleep health management and care is a critical issue in the prevention of cognitive decline in elderly people. Key words: Sleep; Aged; Community health services; Cognition

An algorithm of video network transmission based on unbalanced multiple description coding

More and more embedded systems are emerging based on managed language runtime systems using garbage collected languages such as Java, Python, or the .NET language family. Furthermore, the garbage collection (GC) process is a bottleneck in an embedded system, effectively blocking most other processes including mutator memory access, responding to inputs, or asserting outputs. We demonstrate a valuable new heap memory architecture for garbage collected embedded systems, which works by creating a direct path between memory modules to achieve a two-fold speedup for a memory copy operation as compared to a baseline scenario using multiplexed shared address- and databusses. This direct-path memory setup is generalisable, and memory modules will continue to work as expected when not engaged in garbage collection. The solution space is evaluated by simulating GC activity extracted from the Elephant Track GC tracer. One particular solution is also implemented in hardware to demonstrate the practical realisation of the direct fast copy architecture.

Direct garbage collection: two-fold speedup for managed language embedded systems

More and more embedded systems are emerging based on managed language runtime systems using garbage collected languages such as Java, Python, or the .NET language family. Furthermore, the garbage collection (GC) process is a bottleneck in an embedded system, effectively blocking most other processes including mutator memory access, responding to inputs, or asserting outputs. We demonstrate a valuable new heap memory architecture for garbage collected embedded systems, which works by creating a direct path between memory modules to achieve a two-fold speedup for a memory copy operation as compared to a baseline scenario using multiplexed shared address- and databusses. This direct-path memory setup is generalisable, and memory modules will continue to work as expected when not engaged in garbage collection. The solution space is evaluated by simulating GC activity extracted from the Elephant Track GC tracer. One particular solution is also implemented in hardware to demonstrate the practical realisation of the direct fast copy architecture.

Non-Volatile Memory Based Page Swapping for Building High-Performance Mobile Devices

Smartphones are getting increasingly high-performance with advances in mobile processors and larger main memories to support feature-rich applications. However, the storage subsystem has always been a prohibitive factor that slows down the pace of reaching even higher performance while maintaining good user experience. Despite today's smartphones are equipped with larger-than-ever main memories, they consume more energy and still run out of memory. But the slow NAND flash based storage vetoes the possibility of swapping-an important technique to extend main memory-and leaves a system that constantly terminates user applications under memory pressure. In this paper, we propose NVM-Swap by revisiting swapping for smartphones with fast, byte-addressable, non-volatile memory (NVM) technologies. Instead of using flash, we build the swap area with NVM, to allow high performance without sacrificing user experience. NVM-Swap supports Lazy Swap-in, which can reduce memory copy operations by giving the swapped out pages a second chance to stay in byte-addressable NVM backed swap area. To avoid fast worn-out of certain NVM, we also propose Heap-Wear, a wear leveling algorithm that distributes writes in NVM more evenly. Evaluation results based on the Google Nexus 5 smartphone show that our solution can effectively enhance smartphone performance and achieve better wear-leveling of NVM.

A Halide-based Synergistic Computing Framework for Heterogeneous Systems

New programming models have been developed to embrace contemporary heterogeneous machines, each of which may contain several types of processors, e.g., CPUs, GPUs, FPGAs and ASICs. Unlike the conventional ones, which use separate programming schemes for different processors of the machine, e.g., OpenMP for the CPU and CUDA for the GPU, the new ones tend to offer a unified programming model to abstract details of heterogeneous computing engines. One such programming model is Halide that is designed for high performance image processing. Halide programmers are allowed to map data and computation to either the CPUs or GPUs through high-level C++ functions, which are converted to various code targets, including x86, ARM, CUDA, and OpenCL, by the Halide compiler. Nevertheless, it becomes complex when the programmers attempt to write a Halide program for cooperative computation on both the CPU and GPU. In this work, we propose the synergistic computing framework that extends Halide to improve program execution performance. Several key issues are tackled, including data coherence, workload partitioning, job dispatching and communication/synchronization, so that the Halide programmers are allowed to take advantage of the heterogeneous computing engines with the two developed C++ classes, one is for static workload partitioning/dispatching and the other is the dynamic counterpart. Furthermore, optimizations are developed to improve performance by generating adequate the CPU code, and eliminating extra memory copies. We characterize and discuss the performance of two image processing programs and our framework on the heterogeneous platforms, i.e., Android Nexus 7 smartphone and x86-based computers. Our results show that significant performance gain can be achieved while the CPU and GPU execute a program synergistically with the proposed framework.

NearZero: An Integration of Phase Change Memory with Multi-Core Coprocessor

Multi-core based coprocessors have become powerful research vehicles to analyze a large amount of data. Even though they can accelerate data processing by using a hundred cores, the data unfortunately exist on an external storage device. The separation of computation and storage introduces redundant memory copies and unnecessary data transfers over different physical device boundaries, which limit the benefits of coprocessor-accelerated data processing. In addition, the coprocessors need assistance from host-side resources to access the external storage, which can require additional system context switches. To address these challenges, we propose NearZero, a novel DRAM-less coprocessor architecture that precisely integrates a state-of-the-art phase change memory into its multi-core accelerator. In this work, we implement an FPGA-based memory controller that extracts important device parameters from real phase change memory chips, and apply them to a commercially available hardware platform that employs multiple processing elements over a PCIe fabric. The evaluation results reveal that NearZero achieves on average 47 percent better performance than advanced coprocessor approaches that use direct I/Os (between storage and coprocessors), while consuming only 19 percent of the total energy of such advanced coprocessors.

Energy-Efficient In-Memory Paging for Smartphones

Smartphones are becoming increasingly energy-hungry to support feature-rich applications, posing a lot of pressure on battery lifetime and making energy consumption a non-negligible issue. In particular, dynamic random access memory (DRAM)-based main memory subsystem is a major contributor to the energy consumption of mobile devices. In this paper, we propose direct read (DR). Swap, an energy-efficient in-memory paging design to reduce energy consumption in smartphones. In DR. Swap, we adopt emerging energy-efficient nonvolatile memory (NVM) and use it as the swap area. Utilizing NVMs byte-addressability, we propose DR which guarantees zero memory copy for read-only requests when accessing a page in swap area. To better understand the energy consumption of swapping, we build an energy model to analyze the energy consumption of different paging architectures. We evaluate DR. Swap based on the Google Nexus 5 smartphone, experimental results show that our technique can reduce more than 50% energy consumption compared to DRAM backed swapping.

Embedded multicore computing and applications

Embedded multicore computing and applications

Visual-Motor Maturity and Executive Functions in Schoolchildren

Abstract Visual-motor maturity and executive functions are closely related in the child development process. This study aimed to investigate the relation between visual-motor abilities and executive functions in 83 healthy children between 7 and 10 years old. The tools used were the Bender Gestalt Visual-Motor Test - Gradual Scoring System (B-GSS), Wisconsin Card Sorting Test (WCST), Raven's Progressive Matrices (RPM), and Rey-Osterrieth Complex Figure (ROCF). The correlation between the B-GSS and WCST scores was significantly negative (r = -.23, p &lt; .033), while ROCF variables, such as Total Memory and Total Copy, had a moderate, significant correlation with total B-GSS score (r = -.55, p &lt; .001; r = -.44, p &lt; .001, respectively). The results empirically show the relation between executive functions and visual-motor maturity and are discussed in face of developmental neuropsychology.

Hybrid-optimization strategy for the communication of large-scale Kinetic Monte Carlo simulation

The parallel Kinetic Monte Carlo (KMC) algorithm based on domain decomposition has been widely used in large-scale physical simulations. However, the communication overhead of the parallel KMC algorithm is critical, and severely degrades the overall performance and scalability. In this paper, we present a hybrid optimization strategy to reduce the communication overhead for the parallel KMC simulations. We first propose a communication aggregation algorithm to reduce the total number of messages and eliminate the communication redundancy. Then, we utilize the shared memory to reduce the memory copy overhead of the intra-node communication. Finally, we optimize the communication scheduling using the neighborhood collective operations. We demonstrate the scalability and high performance of our hybrid optimization strategy by both theoretical and experimental analysis. Results show that the optimized KMC algorithm exhibits better performance and scalability than the well-known open-source library—SPPARKS. On 32-node Xeon E5-2680 cluster (total 640 cores), the optimized algorithm reduces the communication time by 24.8% compared with SPPARKS.

Memory Copy Optimization for Streaming Gateway Transcoding: Models and Algorithms

Repeated memory copy during protocol translation inhibits capacity of a streaming media gateway. Unlike existing optimization techniques that rely on platform-specific features, this paper investigates algorithm-level platform-independent strategies. A mathematical concept of the buf-string is proposed to model the protocol transcoding process. Based on this model three payload extraction algorithms that can reduce memory copy are presented. The streaming gateway used in the Next-generation broadcasting (NGB) and the Nextgeneration on-demand (NGOD) system is taken as an example to demonstrate and evaluate our strategies. Experimental results from an x86 host and an embedded system prove that our strategies can reduce CPU overhead by 15% to 45%, and optimize the linear space complexity to a constant one.