Memory Checking Research Articles

FAMILY QUIZZING BEHAVIOR DURING IN-HOME DEMENTIA CARE: A SEQUENTIAL BEHAVIORAL ANALYSIS WITH VIDEO CASE STUDIES

Abstract Quizzing is an understudied communication behavior used by care partners during in-home dementia care interactions. The aim of this study was to characterize and describe the behavior, identify types, characterize care situations, and determine how people living with dementia react to quizzing. Forty video observations of in-home interactions were coded to determine relationships between care partner quizzing and the person with dementia’s reactions and analyzed using sequential behavioral analysis. Ten case studies with high instances of quizzing were examined for interpersonal context. Quizzing was defined as a series of rapid questions by the care partner that most often appeared to test the memory or knowledge of the person with dementia. Instances of quizzing that included long-term and short-term memory checks were most likely to elicit a negative reaction from the person with dementia (resistiveness, distress, and apathy). Long-term memory check always preceded resistiveness and distress (CP=1.0) and apathy preceded long-term memory check short-term memory check (CP = 0.71, 0.21). Quizzing used for distraction or reminiscing appeared to elicit positive responses from the person with dementia. Distraction and mutual reminiscing always followed cooperation (CP=1.0). Case study results indicated the care partners seemed to be testing the abilities of the person with dementia; possibly to alleviate or reverse dementia symptoms. Additional research is warranted to understand the use of quizzing during in-home care. The use of behavioral coding, sequential analysis, and case study examination can provide evidence of communication best practices to develop communication training for dementia care dyads.

Benchmarking Deep Learning Models on Myriad and Snapdragon Processors for Space Applications

Future space missions can benefit from processing imagery on board to detect science events, create insights, and respond autonomously. One of the challenges to this mission concept is that traditional space flight computing has limited capabilities because it is derived from much older computing to ensure reliable performance in the extreme environments of space: particularly radiation. Modern commercial-off-the-shelf processors, such as the Movidius Myriad X and the Qualcomm Snapdragon, provide significant improvements in small size, weight, and power packaging; and they offer direct hardware acceleration for deep neural networks, although these processors are not radiation hardened. We deploy neural network models on these processors hosted by Hewlett Packard Enterprise’s Spaceborne Computer-2 on board the International Space Station (ISS). We find that the Myriad and Snapdragon digital signal processors (DSP)/artificial intelligence processors (AIP) provide speed improvement over the Snapdragon CPU in all cases except single-pixel networks (typically greater than 10 times for DSP/AIP). In addition, the discrepancy introduced through quantization and porting of our Jet Propulsion Laboratory models was usually quite low (less than 5%). Models were run multiple times, and memory checkers were deployed to test for radiation effects. To date, we have found no difference in output between ground and ISS runs, and no memory checker errors.

Screening for Cognitive Impairment with the Quick Memory Check: Validation of a Caregiver Administered Cognitive Screen.

Self or home-administered cognitive screening instruments (CSIs) can reduce barriers to the early detection of mild cognitive impairment (MCI) and dementia. To examine the acceptability and diagnostic accuracy of a caregiver-administered CSI, the Quick Memory Check (QMC). Components of the Quick Mild Cognitive impairment (Qmci) screen (orientation, verbal fluency, and logical memory) were re-weighted to create the QMC, scored out of 100 points. Participants, attending a university hospital memory clinic, were provided administration instructions beforehand. Area under the curve (AUC) scores, adjusted for age and education, were compared with the Qmci screen and Montreal Cognitive Assessment (MoCA). Caregivers or family scored the QMC. In all, 366 participants were recruited; 53 with subjective memory complaints (SMC), 74 with MCI, 193 with dementia, and 46 normal controls. Median QMC scores for controls were 70±13 versus 60±20 for SMC, 52±18 for MCI, and 31±21 for dementia. The QMC had excellent accuracy (AUC 0.97) for cognitive impairment (MCI/dementia from controls), similar to the Qmci screen (AUC 0.98, p = 0.17) and MoCA (AUC 0.95, p = 0.13). At a cut-off of <52/100, the QMC had 83% sensitivity and 100% specificity for cognitive impairment. The QMC had lower accuracy differentiating MCI from SMC (AUC 0.73), albeit similar to the MoCA (AUC 0.70). The QMC, administered by caregivers in advance of clinic, compared favorably to established CSIs scored by trained raters. This caregiver, home-administered CSI is acceptable and can identify cognitive impairment, potentially improving efficiency by reducing testing time and patient stress in busy clinical settings.

The clinical characteristics of patients admitted to the emergency department because of implantable cardioverter defibrillator shock

Aim: To present the clinical spectrum of the Emergency Department (ED) patients with presumed electrical shocks. Material and methods: The electronic recordings of the patients admitted to the ED of Unversity Hospital in Wroclaw between April 2020 and June 2021 were searched for the words: discharge, electrical storm, syncope, con¬vulsions. The received patients recordings were checked and all patients with electrical shocks from implantable cardioverter defibrillators (ICDs) both real and presumed were included into the study. Patients were divided into three groups: patients hospitalized due to adequate ICD discharges, patients hospitalized for other reason who had adequate interventions in the ICD memory and patients with incorrectly diagnosed ICD interventions. Results: The study group consisted of 26 patients. There was 18 men aged 65.9±10.9 and 8 women aged 68.1±12.4 (p=0.66). A total of 20 patients had electrical shocks confirmed by ICD memory checking and 6 patients had no ICD shocks. Conclusions: ED visits due to discharges of ICDs are rare. The medical history of ICD discharge could be misleading, because some patients interpret different symptoms or acoustic signals of the ICDs as a discharge. The ICD patients with syncope, unconsciousness, history of seizures should have their ICD checked for the possible discharges.

ConcurDB: Concurrent Query Authentication for Outsourced Databases

Clients of outsourced databases need Query Authentication (QA) guaranteeing the integrity and authenticity of query results returned by potentially compromised providers. Prior work provides QA assurances for a limited class of queries by deploying several software-based cryptographic constructs. The constructs are often designed assuming read-only or infrequently updated databases. For dynamic datasets, the data owner is required to perform all updates on behalf of clients. Hence, for concurrent updates by multiple clients, such as for OLTP workloads, existing QA solutions are inefficient. We present ConcurDB, a concurrent QA scheme that enables simultaneous updates by multiple clients. To realize concurrent QA, we have designed several new mechanisms. First, we identify and use an important relationship between QA and memory checking to decouple query execution and verification. We allow clients to execute transactions concurrently and perform verifications in parallel using an offline memory checking based protocol. Then, to extend QA to a multi-client scenario, we design new protocols that enable clients to securely exchange a small set of authentication data even when using the untrusted provider as a communication hub. Finally, we overcome provider-side replay attacks. Using ConcurDB, we provide and evaluate concurrent QA for the full TPC-C benchmark. For updates, ConcurDB shows a 4x performance increase over existing solutions.

EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking

Embedded systems are increasingly interconnected in the emerging application scenarios. Many of these applications are safety critical, making it a high priority to ensure that the systems are free from malicious attacks. This work aims to detect vulnerabilities, that could be exploited by adversaries to compromise functional correctness, in the embedded firmware, which is challenging especially due to the absence of source code. In particular, we propose EM-Fuzz, a firmware vulnerability detection technique that tightly integrates fuzzing with real-time memory checking. Based on the memory instrumentation, the firmware fuzzing can not only be guided by the traditional branch coverage to generate high-quality seeds to explore hard-to-reach regions but also by the recorded memory sensitive operations to continuously exercise sensitive regions which are prone to being attacked. More importantly, the instrumentation integrates real-time memory checkers to expose memory vulnerabilities, which is not well-supported by existing fuzzers without source code. The experiments on several real-world embedded firmware such as OpenSSL demonstrate that EM-Fuzz significantly improves the performance of state-of-the-art fuzzing tools, such as AFL and AFLFast, with the coverage improvements of 93.98% and 46.89%, respectively. Furthermore, EM-Fuzz exposes a total of 23 vulnerabilities, with an average of about 7-h per vulnerability. AFL and AFLFast together find 10 vulnerabilities, costing about 13 h and 10-h per vulnerability on average, respectively. Out of these 23 vulnerabilities, 16 are previously unknown and have been reported to the upstream product vendors, 7 of which have been assigned with unique CVE identifiers in the U.S. National Vulnerability Database.

Jury simulation studies: To exclude or not to exclude participants based on a lack of comprehension of the case?

SummaryJury simulation research has been the subject of longstanding criticism in regards to ecological validity. One additional factor that has received little attention that may also impact the generalizability of this research relates to excluding participants based on their memory of, or their attention paid to, the case. In order to determine how common this exclusion is, the authors conducted a scoping review of jury simulation studies within the last 10 years across three major legal psychology journals. The review revealed variability in if and how studies excluded on the basis of poor attention or for failing manipulation or general memory checks. In addition, studies that did exclude on this basis varied greatly in the proportion of the sample that was excluded. Recommendations are provided in order to assist jury researchers in future with how best to manage exclusions on the basis of juror memory and attention.

Performance Analysis of BIST Algorithms

Objective: Performance analyses of March LR and March C- are presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March C- are coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March C- and march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST. Keywords: BIST Algorithm, Built-In-Self-Test (BIST), March C- and March LR, Memory Testing

The CSI Framework for Compiler-Inserted Program Instrumentation

The CSI framework provides comprehensive static instrumentation that a compiler can insert into a program-under-test so that dynamic-analysis tools - memory checkers, race detectors, cache simulators, performance profilers, code-coverage analyzers, etc. - can observe and investigate runtime behavior. Heretofore, tools based on compiler instrumentation would each separately modify the compiler to insert their own instrumentation. In contrast, CSI inserts a standard collection of instrumentation hooks into the program-under-test. Each CSI-tool is implemented as a library that defines relevant hooks, and the remaining hooks are "nulled" out and elided during either compile-time or link-time optimization, resulting in instrumented runtimes on par with custom instrumentation. CSI allows many compiler-based tools to be written as simple libraries without modifying the compiler, lowering the bar for the development of dynamic-analysis tools. We have defined a standard API for CSI and modified LLVM to insert CSI hooks into the compiler's internal representation (IR) of the program. The API organizes IR objects - such as functions, basic blocks, and memory accesses - into flat and compact ID spaces, which not only simplifies the building of tools, but surprisingly enables faster maintenance of IR-object data than do traditional hash tables. CSI hooks contain a "property" parameter that allows tools to customize behavior based on static information without introducing overhead. CSI provides "forensic" tables that tools can use to associate IR objects with source-code locations and to relate IR objects to each other. To evaluate the efficacy of CSI, we implemented six demonstration CSI-tools. One of our studies shows that compiling with CSI and linking with the "null" CSI-tool produces a tool-instrumented executable that is as fast as the original uninstrumented code. Another study, using a CSI port of Google's ThreadSanitizer, shows that the CSI-tool rivals the performance of Google's custom compiler-based implementation. All other demonstration CSI tools slow down the execution of the program-under-test by less than 70%.

The CSI Framework for Compiler-Inserted Program Instrumentation

The CSI framework provides comprehensive static instrumentation that a compiler can insert into a program-under-test so that dynamic-analysis tools - memory checkers, race detectors, cache simulators, performance profilers, code-coverage analyzers, etc. - can observe and investigate runtime behavior. Heretofore, tools based on compiler instrumentation would each separately modify the compiler to insert their own instrumentation. In contrast, CSI inserts a standard collection of instrumentation hooks into the program-under-test. Each CSI-tool is implemented as a library that defines relevant hooks, and the remaining hooks are "nulled" out and elided during either compile-time or link-time optimization, resulting in instrumented runtimes on par with custom instrumentation. CSI allows many compiler-based tools to be written as simple libraries without modifying the compiler, lowering the bar for the development of dynamic-analysis tools. We have defined a standard API for CSI and modified LLVM to insert CSI hooks into the compiler's internal representation (IR) of the program. The API organizes IR objects - such as functions, basic blocks, and memory accesses - into flat and compact ID spaces, which not only simplifies the building of tools, but surprisingly enables faster maintenance of IR-object data than do traditional hash tables. CSI hooks contain a "property" parameter that allows tools to customize behavior based on static information without introducing overhead. CSI provides "forensic" tables that tools can use to associate IR objects with source-code locations and to relate IR objects to each other. To evaluate the efficacy of CSI, we implemented six demonstration CSI-tools. One of our studies shows that compiling with CSI and linking with the "null" CSI-tool produces a tool-instrumented executable that is as fast as the original uninstrumented code. Another study, using a CSI port of Google's ThreadSanitizer, shows that the CSI-tool rivals the performance of Google's custom compiler-based implementation. All other demonstration CSI tools slow down the execution of the program-under-test by less than 70%.

166Screening Tool Performed by Informal Carers, The Quick Memory Check, Correlates with Quick Screen for Mild Cognitive Impairment

166Screening Tool Performed by Informal Carers, The Quick Memory Check, Correlates with Quick Screen for Mild Cognitive Impairment

Using Harmony Search Algorithm for Load Balancing in Cloud Computing

Background: In this paper, we have surveyed the load modification and the trust capability in the cloud computing data centers. Method: The components of harmony search Algorithm include the harmony memory, the pitch adjustment rate and the random selection. The harmony memory checks and selects the responses. HMCR (Harmony Memory Considering Rate) is used for showing the possibility of selection from the memory and the pitch adjustment rate is used for causing a new harmony. Findings: Standard deviation and the resource exploitation average are the most important criteria at the load balancing. In this paper, the proposed Algorithm has been compared with the Genetic Algorithm and the simulation results show that the proposed Algorithm has a better competence than the Genetic Algorithm as the HSD (Harmony Search Degertekin ) rate of the proposed method is less than the HSD rate of Genetic Algorithm and the average of utilization from resources in the proposed method is more as well as with the increasing number of tasks, the performance of the algorithm is improved. Application/Improvement: Using this method of load balancing, the satisfaction of users is maximized, the time of response is minimized and the utilization of resources is increased.

Best bang for your buck: GPU nodes for GROMACS biomolecular simulations.

The molecular dynamics simulation package GROMACS runs efficiently on a wide variety of hardware from commodity workstations to high performance computing clusters. Hardware features are well‐exploited with a combination of single instruction multiple data, multithreading, and message passing interface (MPI)‐based single program multiple data/multiple program multiple data parallelism while graphics processing units (GPUs) can be used as accelerators to compute interactions off‐loaded from the CPU. Here, we evaluate which hardware produces trajectories with GROMACS 4.6 or 5.0 in the most economical way. We have assembled and benchmarked compute nodes with various CPU/GPU combinations to identify optimal compositions in terms of raw trajectory production rate, performance‐to‐price ratio, energy efficiency, and several other criteria. Although hardware prices are naturally subject to trends and fluctuations, general tendencies are clearly visible. Adding any type of GPU significantly boosts a node's simulation performance. For inexpensive consumer‐class GPUs this improvement equally reflects in the performance‐to‐price ratio. Although memory issues in consumer‐class GPUs could pass unnoticed as these cards do not support error checking and correction memory, unreliable GPUs can be sorted out with memory checking tools. Apart from the obvious determinants for cost‐efficiency like hardware expenses and raw performance, the energy consumption of a node is a major cost factor. Over the typical hardware lifetime until replacement of a few years, the costs for electrical power and cooling can become larger than the costs of the hardware itself. Taking that into account, nodes with a well‐balanced ratio of CPU and consumer‐class GPU resources produce the maximum amount of GROMACS trajectory over their lifetime. © 2015 The Authors. Journal of Computational Chemistry Published by Wiley Periodicals, Inc.

Language support for dynamic, hierarchical data partitioning

Applications written for distributed-memory parallel architectures must partition their data to enable parallel execution. As memory hierarchies become deeper, it is increasingly necessary that the data partitioning also be hierarchical to match. Current language proposals perform this hierarchical partitioning statically, which excludes many important applications where the appropriate partitioning is itself data dependent and so must be computed dynamically. We describe Legion, a region-based programming system, where each region may be partitioned into subregions. Partitions are computed dynamically and are fully programmable. The division of data need not be disjoint and subregions of a region may overlap, or alias one another. Computations use regions with certain privileges (e.g., expressing that a computation uses a region read-only) and data coherence (e.g., expressing that the computation need only be atomic with respect to other operations on the region), which can be controlled on a per-region (or subregion) basis. We present the novel aspects of the Legion design, in particular the combination of static and dynamic checks used to enforce soundness. We give an extended example illustrating how Legion can express computations with dynamically determined relationships between computations and data partitions. We prove the soundness of Legion's type system, and show Legion type checking improves performance by up to 71% by eliding provably safe memory checks. In particular, we show that the dynamic checks to detect aliasing at runtime at the region granularity have negligible overhead. We report results for three real-world applications running on distributed memory machines, achieving up to 62.5X speedup on 96 GPUs on the Keeneland supercomputer.

Data Race Detection with Minimal Hardware Support

This article presents AccessedBefore (AccB), an algorithm and its associated minimal hardware support to detect data races, and compares it with two widely known and used commercial tools: Helgrind, the data race detection tool included in the general purpose memory checking suite Valgrind, and Intel Thread Checker, now shipped as part of Intel Thread Inspector. It provides a performance overhead evaluation using current workloads, along with an analysis of AccB's scalability with the number of threads and workload input set size. It demonstrates that AccB is in the range of 2× to 11× faster than these two tools. Finally, it shows the complete proof that AccB is complete in that, for every static data race present in a program, there exists an instruction interleaving that would expose this data race such that AccB can detect it. © 2013 The Author 2013. Published by Oxford University Press on behalf of The British Computer Society. All rights reserved.

Information Cost Tradeoffs for Augmented Index and Streaming Language Recognition

This paper makes three main contributions to the theory of communication complexity and stream computation. First, we present new bounds on the information complexity of augmented-index. In contrast to analogous results for index by Jain, Radhakrishnan, and Sen [J. ACM, 56 (2009), article 33], we have to overcome the significant technical challenge that protocols for augmented-index may violate the “rectangle property” due to the inherent input sharing. Second, we use these bounds to resolve an open problem of Magniez, Mathieu, and Nayak [Proceedings of the 42nd Annual ACM Symposium on Theory of Computing, 2010, pp. 261--270] that asked about the multipass complexity of recognizing Dyck languages. This results in a natural separation between the standard multipass model and the multipass model that permits reverse passes. Third, we present the first passive memory checkers that verify the interaction transcripts of priority queues, stacks, and double-ended queues. We obtain tight upper and lower bounds for these problems, thereby addressing an important subclass of the memory checking framework of Blum et al. [Algorithmica, 12 (1994), pp. 225--244].

What checkers actually check: an eye tracking study of inhibitory control and working memory.

BackgroundNot only is compulsive checking the most common symptom in Obsessive Compulsive Disorder (OCD) with an estimated prevalence of 50–80% in patients, but approximately ∼15% of the general population reveal subclinical checking tendencies that impact negatively on their performance in daily activities. Therefore, it is critical to understand how checking affects attention and memory in clinical as well as subclinical checkers. Eye fixations are commonly used as indicators for the distribution of attention but research in OCD has revealed mixed results at best.Methodology/Principal FindingHere we report atypical eye movement patterns in subclinical checkers during an ecologically valid working memory (WM) manipulation. Our key manipulation was to present an intermediate probe during the delay period of the memory task, explicitly asking for the location of a letter, which, however, had not been part of the encoding set (i.e., misleading participants). Using eye movement measures we now provide evidence that high checkers’ inhibitory impairments for misleading information results in them checking the contents of WM in an atypical manner. Checkers fixate more often and for longer when misleading information is presented than non-checkers. Specifically, checkers spend more time checking stimulus locations as well as locations that had actually been empty during encoding.Conclusions/SignificanceWe conclude that these atypical eye movement patterns directly reflect internal checking of memory contents and we discuss the implications of our findings for the interpretation of behavioural and neuropsychological data. In addition our results highlight the importance of ecologically valid methodology for revealing the impact of detrimental attention and memory checking on eye movement patterns.

A case for unlimited watchpoints

Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit their use to pre-deployment testing, while more advanced systems have such severe performance impacts that they may require special-purpose hardware. Previous works have described hardware that can accelerate individual analyses, but such specialization stymies adoption; generalized mechanisms are more likely to be added to commercial processors. This paper demonstrates that the ability to set an unlimited number of fine-grain data watchpoints can reduce the runtime overheads of numerous dynamic software analysis techniques. We detail the watchpoint capabilities required to accelerate these analyses while remaining general enough to be useful in the future. We describe a hardware design that stores watchpoints in main memory and utilizes two different on-chip caches to accelerate performance. The first is a bitmap lookaside buffer that stores fine-grained watchpoints, while the second is a range cache that can efficiently hold large contiguous regions of watchpoints. As an example of the power of such a system, it is possible to use watchpoints to accelerate read/write set checks in a software data race detector by nearly 9x.

A case for unlimited watchpoints

Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit their use to pre-deployment testing, while more advanced systems have such severe performance impacts that they may require special-purpose hardware. Previous works have described hardware that can accelerate individual analyses, but such specialization stymies adoption; generalized mechanisms are more likely to be added to commercial processors. This paper demonstrates that the ability to set an unlimited number of fine-grain data watchpoints can reduce the runtime overheads of numerous dynamic software analysis techniques. We detail the watchpoint capabilities required to accelerate these analyses while remaining general enough to be useful in the future. We describe a hardware design that stores watchpoints in main memory and utilizes two different on-chip caches to accelerate performance. The first is a bitmap lookaside buffer that stores fine-grained watchpoints, while the second is a range cache that can efficiently hold large contiguous regions of watchpoints. As an example of the power of such a system, it is possible to use watchpoints to accelerate read/write set checks in a software data race detector by nearly 9x.

Processing of order information for numbers and months

Despite a great deal of research on the processing of numerical magnitude (e.g., the quantity denoted by the number 5), few studies have investigated how this magnitude information relates to the ordinal properties of numbers (e.g., the fact that 5 is the fifth integer). In the present study, we investigated order-related processing of numbers, as well as months of the year, with a novel ordering task to see whether the processing of order information differs from the processing of magnitude information. In Experiments 1 and 2, participants were shown three numbers (Experiment 1) or three months (Experiment 2) and were required to indicate whether the stimuli were in the correct order. In Experiment 3, participants were again shown three numbers; however, now they were instructed to indicate whether the three numbers were ordered in a forward, backward, or mixed direction. Whereas number comparison tasks typically reveal distance effects (comparisons become easier with increased distance between two numbers), these three experiments reveal a different pattern of results. There were reverse distance effects when the stimuli crossed a boundary (i.e., when numbers crossed a decade or months crossed the year boundary) and no effect of distance when the stimuli did not cross a boundary (i.e., when numbers were within a decade and months were within the January-December calendar year). These data suggest that additional mechanisms are involved in the processing of order information: a scanning mechanism and a long-term memory checking mechanism.