Memory Access Research Articles

Memory adds no cost to lattice sieving for computers in 3 or more spatial dimensions

The security of lattice-based crytography (LWE, NTRU, and FHE) depends on the hardness of the shortest-vector problem (SVP). Sieving algorithms give the lowest asymptotic runtime to solve SVP, but depend on exponential memory. Memory access costs much more in reality than in the RAM model, so we consider a computational model where processors, memory, and meters of wire are in constant proportions to each other. While this adds substantial costs to route data during lattice sieving, we modify existing algorithms to amortize these costs and find that, asymptotically, a classical computer can achieve the previous RAM model cost of 2 0.2925 d + o ( d ) to sieve a d -dimensional lattice for a computer existing in 3 or more spatial dimensions, and can reach 2 0.3113 d + o ( d ) in 2 spatial dimensions, where “spatial dimensions” are the dimensions of the physical geometry in which the computer exists. Since this result implies an increased cost in 2 spatial dimensions, we make several assumptions about the constant terms of memory access and lattice attacks so that we can give bit security estimates for Kyber and Dilithium. These estimates support but do not increase the security categories claimed in the Kyber and Dilithium specifications, at least with respect to known attacks.

Energy optimization and age of information enhancement in multi‐UAV networks using deep reinforcement learning

AbstractThis letter introduces an innovative approach for minimizing energy consumption in multi‐unmanned aerial vehicles (multi‐UAV) networks using deep reinforcement learning, with a focus on optimizing the age of information (AoI) in disaster environments. A hierarchical UAV deployment strategy that facilitates cooperative trajectory planning, ensuring timely data collection and transmission while minimizing energy consumption is proposed. By formulating the inter‐UAV network path planning problem as a Markov decision process, a deep Q‐network (DQN) strategy is applied to enable real‐time decision making that accounts for dynamic environmental changes, obstacles, and UAV battery constraints. The extensive simulation results, conducted in both rural and urban scenarios, demonstrate the effectiveness of employing a memory access approach within the DQN framework, significantly reducing energy consumption up to 33.25% in rural settings and 74.20% in urban environments compared to non‐memory approaches. By integrating AoI considerations with energy‐efficient UAV control, this work offers a robust solution for maintaining fresh data in critical applications, such as disaster response, where ground‐based communication infrastructures are compromised. The use of replay memory approach, particularly the online history approach, proves crucial in adapting to changing conditions and optimizing UAV operations for both data freshness and energy consumption.

GPU parallel implementation of a finite volume lattice Boltzmann method for incompressible flows

This work presents a graphics processing units (GPU) parallel algorithm of a cell-centered finite volume lattice Boltzmann method (FVLBM) on unstructured meshes. In the present GPU parallel algorithm, the parallelization is performed in the physical space. To reduce the frequency of GPU memory accesses, this algorithm develops coalesced access to GPU memory. In addition, to avoid the race for resources leading to data anomalies, such as dirty read or phantom read etc., and the double counting for flux calculation, the efficient face-based data structure often used for flux calculation in cells in the central processing unit (CPU) version of FVLBM is modified into a face-based data structure used for the fluxes on all faces, followed by a cell-based loop for the final residuals in all cells. Therefore, the proposed GPU parallel algorithm does not need to use the resource lock and retains the high efficiency of the face-based data structure in the fluxes computation to enhance its’ parallel efficiency. Additionally, to demonstrate the computational efficiency of the proposed GPU parallel algorithm, various benchmark studies are performed in this work by the proposed parallel scheme on a double precision NVIDIA GeForce RTX 3090Ti GPU card, including (a) the lid-driven flow in a two-dimensional (2D) square cavity, (b) a 2D flow past a cylinder, and (c) the lid-driven flow in a three-dimensional (3D) cubic cavity. The numerical results show that the proposed GPU parallel algorithm can be as accurate as the original CPU serial scheme with 1 to 2 orders of speedup.

Bud-YOLO: A Real-Time Accurate Detection Method of Cotton Top Buds in Cotton Fields

Cotton topping plays a crucial and indispensable role in controlling excessive growth and enhancing cotton production. This study aims to improve the operational efficiency and accuracy of cotton topping robots through a real-time and accurate cotton top bud detection algorithm tailored for field operation scenarios. We propose a lightweight structure based on YOLOv8n, replacing the C2f module with the Cross-Stage Partial Networks and Partial Convolution (CSPPC) module to minimize redundant computations and memory access. The network’s neck employs an Efficient Reparameterized Generalized-FPN (Efficient RepGFPN) to achieve high-precision detection without substantially increasing computational cost. Additionally, the loss calculation of the optimized prediction frame was addressed with the Inner CIoU loss function, thereby enhancing the precision of the model’s prediction box. Comparison experiments indicate that the Bud-YOLO model is highly effective for detecting cotton top buds, with an AP50 of 99.2%. This performance surpasses that of other YOLO variants, such as YOLOv5s and YOLOv10n, as well as the conventional Faster R-CNN model. Moreover, the Bud-YOLO model exhibits robust performance across various angles, occlusion conditions, and bud morphologies. This study offers technical insights to support the migration and deployment of the model on cotton topping machinery.

Correction to “I forgot that you existed: Role of memory accessibility in the gender citation gap” by Yan et al. (2024).

Correction to “I forgot that you existed: Role of memory accessibility in the gender citation gap” by Yan et al. (2024).

Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication

Stream processing, which involves real-time computation of data as it is created or received, is vital for various applications, specifically wireless communication. The evolving protocols, the requirement for high-throughput, and the challenges of handling diverse processing patterns make it demanding. Traditional platforms grapple with meeting real-time throughput and latency requirements due to large data volume, sequential and indeterministic data arrival, and variable data rates, leading to inefficiencies in memory access and parallel processing. We present Canalis, a throughput-optimized framework designed to address these challenges, ensuring high-performance while achieving low energy consumption. Canalis is a hardware-software co-designed system. It includes a programmable spatial architecture, FluxSPU (Flux Stream Processing Unit), proposed by this work to enhance data throughput and energy efficiency. FluxSPU is accompanied by a software stack that eases the programming process. We evaluated Canalis with eight distinct benchmarks. When compared to CPU and GPU in mobile SoC to demonstrate the effectiveness of domain specialization, Canalis achieves an average speedup of 13.4× and 6.6×, and energy savings of 189.8× and 283.9×, respectively. In contrast to equivalent ASICs of the benchmarks, the average energy overhead of Canalis is within 2.4×, successfully maintaining generalizations without incurring significant overhead.

DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS

Rapid growth in data size poses significant computational and memory challenges to data processing. FPGA accelerators and near-storage processing have emerged as compelling solutions for tackling the growing computational and memory requirements. Many FPGA-based accelerators have shown to be effective in processing large data sets by leveraging the storage capability of either host-attached or FPGA-attached storage devices. However, the current HLS development environment does not allow direct access to host-or FPGA-attached NVMe storage from the HLS code. As such, users must frequently hand off between HLS and host code to access data in storage, and such a process requires tedious programming to ensure functional correctness. Moreover, since the HLS code uses radically different methods to access storage compared to DRAM, the HLS codebase targeting DRAM-based platforms cannot be easily ported to NVMe-based platforms, resulting in limited code portability and reusability. Furthermore, frequent suspension of HLS kernel and synchronization between CPU and FPGA introduce significant latency overhead and require sophisticated scheduling mechanisms to hide latency. To address these challenges, we propose a new HLS storage interface named DONGLE 2.0 that enables direct FPGA-orchestrated NVMe storage access. By providing a unified interface for storage and memory access, DONGLE 2.0 allows a single-source HLS program to target multiple memory/storage devices, thus making the codebase cleaner, portable, and more efficient. DONGLE 2.0 is an extension to DONGLE 1.0 [ 1 ] but adds support for host-attached storage. While its primary focus is still on FPGA NVMe access in near-storage configurations, the added host storage support ensures its compatibility with platforms that lack native support for FPGA-attached NVMe storage. We implemented a prototype of DONGLE 2.0 using an AMD/Xilinx Alveo U200 FPGA and Solidigm DC-P4610 SSD. Our evaluation on various workloads showed a geometric mean speed-up of 2.3× and a reduction in lines of code (LoC) by 2.4× compared to the state-of-the-art commercial platform when using FPGA-attached NVMe storage. Moreover, DONGLE 2.0 demonstrated a geometric mean speed-up of 1.5× and a reduction in LoC by 2.4× compared to the state-of-the-art commercial platform when using host-attached NVMe storage.

L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform

Due to the high complexity of constructing exact k -nearest neighbor graphs, approximate construction has become a popular research topic. The NN-Descent algorithm is one of the representative in-memory algorithms. To effectively handle large datasets, existing state-of-the-art solutions combine the divide-and-conquer approach and the NN-Descent algorithm, where large datasets are divided into multiple partitions, and a subgraph is constructed for each partition before all the subgraphs are merged, reducing the memory pressure significantly. However, such solutions fail to address inefficiencies in large-scale k -nearest neighbor graph construction. In this paper, we propose L-FNNG, a novel solution for accelerating large-scale k -nearest neighbor graph construction on CPU-FPGA heterogeneous platform. The CPU is responsible for dividing data and determining the order of partition processing, while the FPGA executes all construction tasks to utilize the acceleration capability fully. To accelerate the execution of construction tasks, we design an efficient FPGA accelerator, which includes the Block-based Scheduling (BS) and Useless Computation Aborting (UCA) techniques to address the problems of memory access and computation in the NN-Descent algorithm. We also propose an efficient scheduling strategy that includes a KD-tree-based data partitioning method and a hierarchical processing method to address scheduling inefficiency. We evaluate L-FNNG on a Xilinx Alveo U280 board hosted by a 64-core Xeon server. On multiple large-scale datasets, L-FNNG achieves, on average, 2.3× construction speedup over the state-of-the-art GPU-based solution.

Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access

The growing memory demands of modern applications have driven the adoption of far memory technologies in data centers to provide cost-effective, high-capacity memory solutions. However, far memory presents new performance challenges because its access latencies are significantly longer and more variable than local DRAM. For applications to achieve acceptable performance on far memory, a high degree of memory-level parallelism (MLP) is needed to tolerate the long access latency. While modern out-of-order processors are capable of exploiting a certain degree of MLP, they are constrained by resource limitations and hardware complexity. The key obstacle is the synchronous memory access semantics of traditional load/store instructions, which occupy critical hardware resources for a long time. The longer far memory latencies exacerbate this limitation. This article proposes a set of Asynchronous Memory Access Instructions (AMI) and its supporting function unit, Asynchronous Memory Access Unit (AMU), inside contemporary Out-of-Order Core. AMI separates memory request issuing from response handling to reduce resource occupation. Additionally, AMU architecture supports up to several hundreds of asynchronous memory requests through re-purposing a portion of L2 Cache as scratchpad memory (SPM) to provide sufficient temporal storage. Together with a coroutine-based programming framework, this scheme can achieve significantly higher MLP for hiding far memory latencies. Evaluation with a cycle-accurate simulation shows AMI achieves 2.42× speedup on average for memory-bound benchmarks with 1μs additional far memory latency. Over 130 outstanding requests are supported with 26.86× speedup for GUPS (random access) with 5 μs latency. These demonstrate how the techniques tackle far memory performance impacts through explicit MLP expression and latency adaptation.

Kibernetski napadi preko stranskih kanalov

When implementing cryptographic primitives in software, we often resort to optimizing the software code in order to reduce unnecessary computation time. Such decisions can have negative consequences on data leakage outside the implementation. Attackers can exploit the additional information generated by the execution of the software solution in a way that gives them additional insights into the operation of the software, the values calculated and access to the data itself. Insights can be gained in the form of execution time, memory access patterns, power consumption, and other seemingly unrelated system parameters. Such attacks are referred to as “side-channel attacks”. This paper presents several examples of such attacks and the magnitude of information leakage, as well as how to protect against such attacks. Time-based cryptanalysis, power-based cryptanalysis, including a special variant – video-based cryptanalysis – and memory-based cryptanalysis are described. A simple timing cryptanalysis attack is used as an example to present the analysis process and the results before and after the implementation of the proposed mitigation. Članek predstavlja več primerov takšnih napadov in razsežnosti uhajanja informacij ter načinov zaščite pred napadi. Opisane so časovna kriptoanaliza, kriptoanaliza na podlagi porabe energije in njena posebna različica -- kriptoanaliza na podlagi videoposnetka -- ter pomnilniška kriptoanaliza. Na primeru preprostega napada s časovno kriptoanalizo je predstavljen postopek analize in rezultati pred in po implementaciji predlagane zaščite.

Insulation Detection Algorithm for Gloves Based on Improved YOLOv8n

With the rapid development of China's industry, the safety problems in the process of electrical operation are highly concerned by the electrical industry. In order to reduce the incidence of electrical safety accidents, it is very necessary to wear insulating gloves for electric power construction, which is also of great significance to ensure the safety of electric power production. However, the small target of insulating gloves and the complexity of the electrician operation site, which undoubtedly increases the difficulty of identifying the algorithm model of insulating gloves. For this problem, insulation glove target detection algorithm based on YOLOv8n improvement model. Through many experiments, YOLOv8n was selected as the basic framework of the insulating glove detection algorithm. In order to make the model more accurately locate and identify the targets of interest, the efficient coordinate attention mechanism Coordinate Attention was inserted into backbone to improve the accuracy of the model. The introduction of PConv in necbricks reduces redundant computation and memory access for a more efficient extraction of spatial features. After the improved YOLOv8n algorithm, the mAP is increased from the initial 96.4% to 98.6%, which provides a good reference value for the subsequent research of the target detection algorithm of insulating gloves.

Acceleration of Tensor-Product Operations with Tensor Cores

In this paper, we explore the acceleration of tensor product operations in finite element methods, leveraging the computational power of the NVIDIA A100 GPU Tensor Cores. We provide an accessible overview of the necessary mathematical background and discuss our implementation strategies. Our study focuses on two common programming approaches for NVIDIA Tensor Cores: the C++ Warp Matrix Functions in nvcuda::wmma and the inline Parallel Thread Execution (PTX) instructions mma.sync.aligned . A significant focus is placed on the adoption of the versatile inline PTX instructions combined with a conflict-free shared memory access pattern, a key to unlocking superior performance. When benchmarked against traditional CUDA Cores, our approach yields a remarkable 2.3-fold increase in double precision performance, achieving 8 TFLOPS/s—45% of the theoretical maximum. Furthermore, in half-precision computations, numerical experiments demonstrate a fourfold enhancement in solving the Poisson equation using the flexible GMRES (FGMRES) method, preconditioned by a multigrid method in 3D. This is achieved while maintaining the same discretization error as observed in double precision computations. These results highlight the considerable benefits of using Tensor Cores for finite element operators with tensor products, achieving an optimal balance between computational speed and precision.

Effects of color-flavor association on visual search process for reference pictures on beverage packaging: behavioral, electrophysiological, and causal mechanisms.

The visual search for product packaging involves intricate cognitive processes that are prominently impacted by learned associations derived from extensive long-term experiences. The present research employed EEG technology and manipulated the color display of reference pictures on beverage bottles to explore the underlying neurocognitive pathways. Specifically, we aimed to investigate the influence of color-flavor association strength on the visual processing of such stimuli as well as the in-depth neural mechanisms. The behavioral results revealed that stimuli with strong association strength triggered the fastest response and the highest accuracy, compared with the stimuli with weak association strength and the achromatic ones. The EEG findings further substantiated that the chromatic stimuli evoked a more pronounced N2 component than achromatic ones, and the stimuli with strong association strength elicited larger P3 and smaller N400 amplitudes than the ones with weak association strength. Additionally, the source localization using sLORETA showed significant activations in the inferior temporal gyrus. In conclusion, our research suggests that (1) color expectations would guide visual search process and trigger faster responses to congruent visual stimuli, (2) both the initial perceptual representation and subsequent semantic representation play pivotal roles in effective visual search for the targets, and (3) the color-flavor association strength potentially exerts an impact on visual processing by modulating memory accessibility.

SpQuant-SNN: ultra-low precision membrane potential with sparse activations unlock the potential of on-device spiking neural networks applications.

Spiking neural networks (SNNs) have received increasing attention due to their high biological plausibility and energy efficiency. The binary spike-based information propagation enables efficient sparse computation in event-based and static computer vision applications. However, the weight precision and especially the membrane potential precision remain as high-precision values (e.g., 32 bits) in state-of-the-art SNN algorithms. Each neuron in an SNN stores the membrane potential over time and typically updates its value in every time step. Such frequent read/write operations of high-precision membrane potential incur storage and memory access overhead in SNNs, which undermines the SNNs' compatibility with resource-constrained hardware. To resolve this inefficiency, prior works have explored the time step reduction and low-precision representation of membrane potential at a limited scale and reported significant accuracy drops. Furthermore, while recent advances in on-device AI present pruning and quantization optimization with different architectures and datasets, simultaneous pruning with quantization is highly under-explored in SNNs. In this work, we present SpQuant-SNN, a fully-quantized spiking neural network with ultra-low precision weights, membrane potential, and high spatial-channel sparsity, enabling the end-to-end low precision with significantly reduced operations on SNN. First, we propose an integer-only quantization scheme for the membrane potential with a stacked surrogate gradient function, a simple-yet-effective method that enables the smooth learning process of quantized SNN training. Second, we implement spatial-channel pruning with membrane potential prior, toward reducing the layer-wise computational complexity, and floating-point operations (FLOPs) in SNNs. Finally, to further improve the accuracy of low-precision and sparse SNN, we propose a self-adaptive learnable potential threshold for SNN training. Equipped with high biological adaptiveness, minimal computations, and memory utilization, SpQuant-SNN achieves state-of-the-art performance across multiple SNN models for both event-based and static image datasets, including both image classification and object detection tasks. The proposed SpQuant-SNN achieved up to 13× memory reduction and >4.7× FLOPs reduction with < 1.8% accuracy degradation for both classification and object detection tasks, compared to the SOTA baseline.

Enhancing QoS in Multicore Systems with Heterogeneous Memory Configurations

Quality of service (QoS) has evolved to ensure performance across various computing environments, focusing on data bandwidth, response time, throughput, and stability. Traditional QoS schemes primarily target DRAM-based homogeneous memory systems, exposing limitations when applied to diverse memory configurations. Moreover, the emergence of nonvolatile memories (NVMs) has made achieving QoS even more challenging due to their differing characteristics. While QoS schemes have been proposed for DRAM-based memory systems or hybrid memory systems combining DRAM and a single NVM type, there is a lack of research on QoS techniques for memory systems that incorporate multiple types of NVM simultaneously. Ensuring QoS in these heterogeneous memory environments is challenging due to significant differences in memory characteristics. In this paper, we propose a novel technique, dynamic affinity-based resource pairing (DARP), designed to enhance QoS in multicore heterogeneous memory systems. The proposed approach dynamically monitors the memory access patterns of applications and leverages the specific read/write characteristics of NVM devices. Detailed information from monitoring is used to optimally allocate memory data to the most suitable memory devices, ensuring stable memory response times and mitigating bottlenecks. Extensive experiments validate the efficiency and scalability of DARP across various workloads and heterogeneous memory configurations, including memory systems with multiple types of NVM. The results show that our technique significantly outperforms state-of-the-art QoS methods in terms of memory response time consistency and overall QoS in heterogeneous memory environments. DARP achieved a memory response time variability of 74.4% in six different memory configurations compared to the baseline on average, demonstrating its high scalability and effectiveness in enhancing QoS across various heterogeneous memory systems.

Refactoring the elastic–viscous–plastic solver from the sea ice model CICE v6.5.1 for improved performance

Abstract. This study focuses on the performance of the elastic–viscous–plastic (EVP) dynamical solver within the sea ice model, CICE v6.5.1. The study has been conducted in two steps. First, the standard EVP solver was extracted from CICE for experiments with refactored versions, which are used for performance testing. Second, one refactored version was integrated and tested in the full CICE model to demonstrate that the new algorithms do not significantly impact the physical results. The study reveals two dominant bottlenecks, namely (1) the number of Message Parsing Interface (MPI) and Open Multi-Processing (OpenMP) synchronization points required for halo exchanges during each time step combined with the irregular domain of active sea ice points and (2) the lack of single-instruction, multiple-data (SIMD) code generation. The standard EVP solver has been refactored based on two generic patterns. The first pattern exposes how general finite differences on masked multi-dimensional arrays can be expressed in order to produce significantly better code generation by changing the memory access pattern from random access to direct access. The second pattern takes an alternative approach to handle static grid properties. The measured single-core performance improvement is more than a factor of 5 compared to the standard implementation. The refactored implementation of strong scales on the Intel® Xeon® Scalable Processors series node until the available bandwidth of the node is used. For the Intel® Xeon® CPU Max series, there is sufficient bandwidth to allow the strong scaling to continue for all the cores on the node, resulting in a single-node improvement factor of 35 over the standard implementation. This study also demonstrates improved performance on GPU processors.

HashGrid: An optimized architecture for accelerating graph computing on FPGAs

Large-scale graph processing poses challenges due to its size and irregular memory access patterns, causing performance degradation in common architectures, such as CPUs and GPUs. Recent research includes accelerating graph processing using Field Programmable Gate Arrays (FPGAs). FPGAs can provide very efficient acceleration thanks to reconfigurable on-chip resources. Although limited, these resources offer a larger design space than CPUs and GPUs.We propose an approach in which data are preprocessed in small chunks with an optimized graph partitioning technique for execution on FPGA accelerators. The chunks, located on the host, are streamed directly into a customized memory layer implemented in the FPGA, which is tightly coupled with the processing elements responsible for the graph algorithm execution. This improves application memory access latency, which is crucial in large-sale graph computing performance.This work presents a hardware design that, combined with graph partitioning, enables us to achieve high-performance and potentially scalable handling of large graphs (i.e., graphs with millions of vertices and billions of edges in current scenarios) while using popular graph algorithms. The proposed framework accelerates performance 56 times compared with CPU (multicore with 16 logical cores in our reference experiments), 2.5 times and 4 times faster compared to state-of-the-art FPGA and GPU solutions (FPGA has 15 compute units, and GPU reference has 128 streaming-multiprocessors in our experiments), respectively, when using the PageRank algorithm. For the Single-Source-Shortest-Past (SSSP) algorithm, we achieve speedups of up to 65x, 26x, and 18x compared to CPU, GPU, and FPGA works, respectively. Lastly, in the context of the Weakly Connected Component (WCC) algorithm, our framework achieves a speedup of up to 403 times compared to the CPU, 7.4x against the GPU, and it is faster than the FPGA alternatives up to 10.3x.

SARDIMM: High-Speed Near-Memory Processing Architecture for Synthetic Aperture Radar Imaging

The range-Doppler algorithm (RDA), a key technique for generating synthetic aperture radar (SAR) images, offers high-resolution images but requires significant memory resources and involves complex signal processing. Moreover, the multitude of fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) operations in RDA necessitates high bandwidth and lacks data reuse, leading to bottlenecks. This paper introduces a synthetic aperture radar dual in-line memory module (SARDIMM), which executes RDA operations near memory via near-memory processing (NMP), thereby effectively reducing memory accesses, execution time, and energy consumption. The embedded NMP module in SARDIMM optionally supports a combination of FFT, IFFT, and matched filter operations of the RDA for range and azimuth compression. The operator within the NMP module accelerates the FFT by performing two radix-2 single butterfly operations in parallel. The NMP module was implemented and validated on a Xilinx UltraScale+ field-programmable gate array (FPGA) using Verilog-HDL. The acceleration performance of RDA for images of various sizes was evaluated through a simulator modified with gem5 and DRAMSim3 and achieved a 6.34–6.93× speedup and 41.9–48.2% energy savings.

Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product

Sparse-dense matrix multiplication (SpMM) is the performance bottleneck of many high-performance and deep-learning applications, making it attractive to design specialized SpMM hardware accelerators. Unfortunately, existing hardware solutions do not take full advantage of data reuse opportunities of the input and output matrices or suffer from irregular memory access patterns. Their strategies increase the off-chip memory traffic and bandwidth pressure, leaving much room for improvement. We present Mentor , a new approach to designing SpMM accelerators. Our key insight is that column-wise dataflow, while rarely exploited in prior works, can address these issues in SpMM computations. Mentor is a software-hardware co-design approach for leveraging column-wise dataflow to improve data reuse and regular memory accesses of SpMM. On the software level, Mentor incorporates a novel streaming construction scheme to preprocess the input matrix for enabling a streaming access pattern. On the hardware level, it employs a fully pipelined design to unlock the potential of column-wise dataflow further. The design of Mentor is underpinned by a carefully designed analytical model to find the trade-off between performance and hardware resources. We have implemented an FPGA prototype of Mentor . Experimental results show that Mentor achieves speedup by geomean 2.05 × (up to 3.98 ×), reduces the memory traffic by geomean 2.92 × (up to 4.93 ×), and improves bandwidth utilization by geomean 1.38 × (up to 2.89 ×), compared to the state-of-art hardware solutions.

An efficient ANN SoC for detecting Alzheimer's disease based on recurrent computing

Alzheimer's Disease (AD) is an irreversible, degenerative condition that, while incurable, can have its progression slowed or impeded. While there are numerous methods utilizing neural networks for AD detection, there is a scarcity of High-performance AD detection chips. Moreover, excessively complex neural networks are not conducive to on-chip implementation and clinical applications. This study addresses the challenges of high misdiagnosis rates and significant hardware costs inherent in traditional AD detection techniques. A novel and efficient AD detection framework based on a recurrent computational strategy is proposed. The framework harnesses an Artificial Neural Network (ANN) embedded within a System on Chip (SoC) to perform sophisticated Electroencephalogram (EEG) analysis. The approach began by employing a reduced IEEE754 single-precision encoding method to hardware-encode the preprocessed EEG data, thereby minimizing the memory storage area. Next, data remapping techniques were utilized to ensure the continuity of the input data read addresses and reduce the memory access pressure during neural network computations. Subsequently, hierarchical and Processing Element (PE) reuse technologies were leveraged to perform the multiply-accumulate operations of the ANN. Finally, a step function was chosen to establish binary classification circuits dedicated to AD detection. Experimental results indicate that the optimized SoC achieves a 70 % reduction in area and a 50 % reduction in power consumption compared to traditional designs. For various neural network models, the detection model proposed in this paper incurs less overhead, with a training speed 3 to 4 times faster than other traditional models, and a high accuracy rate of 98.53 %.