Memory Access Methods Research Articles

Implementation of a direct-addressing based lattice Boltzmann GPU solver for multiphase flow in porous media

GPU accelerated lattice Boltzmann (LB) simulations of multiphase flow in porous media have become a powerful tool to study fluid displacement process in porous media. For porous structures with a very low porosity, indirect-addressing memory access methods are preferred due to significantly reduction of the memory footprint despite that those methods are more difficult to implement and the resulting performance may be more sensible to the computing architectures, such as cache hierarchy and size. The direct-addressing methods are straightforward to implement and are able to archive high throughput when the porosity is large, while the methods become less efficient when the structures are too sparse. Nevertheless, the direct-addressing methods combined with multi-block grid technique are promising for many applications. In this work, we present a hybrid-way to tackle multiphase flow simulations in porous media, where the direct-addressing method is employed for the main LB evolution while the indirect-addressing method is employed for the complex boundary conditions. The CSF-based LB color-gradient multiphase model and the geometry-based wetting model are employed to increase accuracy and stability. Thanks to the utilization of AA-pattern streaming scheme, non-slip boundary condition of arbitrary orientation can be enforced without extra cost. We perform comprehensive analysis of the computational performance of the present solver on NVIDIA GPUs. For typical sandstones, our results show that the present implementation is able to achieve over 1.5 speedup compared with other direct-addressing schemes on V100 and A100, respectively and, particularly, the computational performance of the boundary kernels is greatly increased thanks to the increased L2 cache size of the latest GPUs.

Data Alignment on Embedded CPUs for Programmable Control Devices

This work aims to investigate the impact of memory access limitations in microcontrollers and microprocessors on the performance of software that deals with binary data. The research area covers control systems that process data from the IEC 61131-3 standard using a software-implemented virtual machine. Three methods of memory access are considered, namely byte access, memory copying, and direct pointer. Tests of these methods are performed on several CPUs with ARM architecture (with variants), MIPS, RISC-V, Quark, and others, often used as hardware platforms for control devices. The tests cover 1-, 2-, 4-, and 8-byte data sizes, which correspond to the integer types of the IEC 61131-3 standard. By analyzing the results covering both unaligned and aligned data, the goal of this paper is to indicate which of the memory access methods is the most efficient for a particular platform. The research is supplemented with an evaluation of power and memory requirements for a group of STM32 microcontrollers. Therefore, the contribution of this paper rests in indicating the most efficient memory access method for each of more than a dozen CPUs intended for control applications, with consideration of power and memory requirements.

Ordered Access Memory and Its Application in Parallel Processors

In this paper, after analyzing the known memory access methods, conventional memory organization and its challenging problems, we propose new ordered memory access method and a new type of memory – the ordered access memory. This method is aimed at working with data arrays and provides memory access in the prescribed manner. Proposed method unlike widely used method of sequential memory access allows extending the functionality of the memory as it provides not only sequential, but also any other ordered memory access. Unlike another widely used method of address memory access, the implementation of the proposed method provides parallel conflict-free memory access. It also allows eliminating data binding to a specific memory location that makes it possible to disintegrate the apparatus for data ordering and eliminates the need to store addresses of locations the data are placed in, and the need to submit the address to the address inputs during data writing and reading. The new method distinctive features compared to the known memory access methods are considered. Input data, their indices and output data of the ordered access memory are described as well as the approaches to this type of memory design and use. The interface of the ordered access memory is considered as well as its advances compared to the random, associative, and sequential access memories. An example of the ordered access memory usage in application-specific processors with parallel and pipeline structures is demonstrated and the results of the ordered access memory implementation in FPGA are considered.

FPGA, GPU, and CPU implementations of Jacobi algorithm for eigenanalysis

Parallel implementations of Jacobi algorithm for eigenanalysis of a matrix on most commonly used high performance computing (HPC) devices such as central processing unit (CPU), graphics processing unit (GPU), and field-programmable gate array (FPGA) are discussed in this paper. Their performances are investigated and compared. It is shown that CPU, even with multi-threaded implementation, is not a feasible option for large dense matrices. For the GPU implementation, performance impact of the global memory access patterns on the GPU board and the memory coalescing are emphasized. Three memory access methods are proposed. It is shown that one of them achieves 81.6% computational performance improvement over the traditional GPU methods, and it runs 68.5 times faster than a single-threaded CPU for a dense symmetric square matrix of size 1,024. Furthermore, FPGA implementation is presented and its performance running on chips from two major manufacturers are reported. A comparison of GPU and FPGA implementations is quantified and ranked. It is reported that FPGA design delivers the best performance for such a task while GPU is a strong competitor requiring less development effort with superior scalability. We predict that emerging big data applications will benefit from real-time and high performance computing implementations of eigenanalysis for information inference and signal analytics in the future.

고속 홀로그램 생성 하드웨어를 위한 메모리 접근

In this paper we analysis for in out signal by previous study and implement virtual master that generate CGH processor signals. Also, we propose memory address mapping. By constructing the system model of our method and by analyzing the latencies according to the memory access methods in a system including our model and several other models, the low-latency memory access method has been obtained. The proposed method is reduce number of activation in DRAM.

A C-Based Variable Length and Vector Pipeline Architecture Design Methodology and Its Application

The size and performance of a System LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the System LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based variable length and vector pipeline (VVP) architecture design methodology and apply it to the design of the output probability computation circuit for a speech recognition system. VVP processing accelerated by loop optimization, memory access methods, and application-specific cir- cuit design was implemented to calculate the Hidden Markov Model (HMM) output probability at high speed and its performance is evaluated. It is shown that designers can explore a wide range of design choices and generate complex circuits in a short time by using a C-based pipeline architecture design method.

Guest Editor's Introduction: Special Section on Challenges and Solutions in Multicore and Many‐Core Computing

Guest Editor's Introduction: Special Section on Challenges and Solutions in Multicore and Many‐Core Computing

Generating optimal CUDA sparse matrix–vector product implementations for evolving GPU hardware

SUMMARYThe CUDA model for graphics processing units (GPUs) presents the programmer with a plethora of different programming options. These includes different memory types, different memory access methods and different data types. Identifying which options to use and when is a non‐trivial exercise. This paper explores the effect of these different options on the performance of a routine that evaluates sparse matrix–vector products (SpMV) across three different generations of NVIDIA GPU hardware. A process for analysing performance and selecting the subset of implementations that perform best is proposed. The potential for mapping sparse matrix attributes to optimal CUDA SpMV implementations is discussed. Copyright © 2011 John Wiley & Sons, Ltd.

Direct memory access methods applied to chaotic behavior experiments

This paper deals with the implementation of a PC-controlled benchmark specially suited to real-time experimental investigation of oscillators driven by impulsive parametric pulses. The benchmark performs both the acquisition of the output signal and the generation of the parametric pulses. It also allows the introduction of a programmable delay to investigate its influence on the dynamics of the oscillator. The time required for the building of each pulse has been reduced from 10 ms (typical setting time of a standard programmable generator) to 15 /spl mu/s, employing the standard PC's direct memory access (DMA) transfer and pulse generation capabilities, allowing the investigation of oscillators with relevant frequency content up to 30 kHz.