Mbit Dynamic Random Access Memory Research Articles

Development of New Advanced Resist Materials for Microlithography

This paper reviews development of advanced resist materials which I have been involved in for more than a quarter century. First, our attempts to increase the main chain scission susceptibility are described. Next, a simple lift-off process for fabrication of magnetoresistive heads for storage devices is presented, which became the industry-standard manufacturing technology. Then, the major focus is going to be placed on the development of chemical amplification resists. Chemical amplification resists achieve a high sensitivity through a catalytic action of a photochemically generated acid. This drastically novel imaging concept was considered laboratory curiosity initially. However, the very first chemically amplified tBOC resist was quickly implemented in mass production of 1 megabit dynamic random access memory devices by deep UV lithography at IBM. Since then the chemical amplification concept has become the paradigm of advanced resist systems, enabling the industry to continue to migrate to shorter wavelengths (from 365 to 248, and then to 193 nm) for higher resolution and to follow the Moore's law. The chemical amplification resist invented for 1 μm resolution can now resolve

Chemical Amplification Resists: Laboratory Curiosity to Paradigm

It has been a little more than a quarter century since chemical amplification resists were invented. They achieve a high sensitivity through a catalytic action of a photochemically generated acid. This drastically novel imaging concept was considered laboratory curiosity initially. However, the very first chemically amplified tBOC resist was quickly implemented in mass production of 1 megabit dynamic random access memory devices by deep UV lithography at IBM. Since then the chemical amplification concept has become the paradigm of advanced resist systems, enabling the industry to shift to shorter wavelengths (from 365 to 248, and then to 193 nm) for higher resolution and to follow the Moore's law. The chemical amplification resist invented for 1 μm resolution can now resolve 30 nm equal line/space patterns and continues to play a pivotal role in microlithography in the foreseeable future. This paper describes the inception and advancement of chemical amplification resists.

Measurement of Single-Event Effects on a Large Number of Commercial DRAMs

To evaluate the characteristics of commercial memory devices for space use, the Japan Aerospace Exploration Agency (JAXA) launched a Solid State Recorder (SSR) on the Mission Demonstration test Satellite-1 (MDS-1 or 'Tsubas') into geo-stationary transfer orbit (GTO) in February 2002. Passing through the radiation belt exposed the MDS-1 to severe radiation environment in every orbit. This flight experiment allowed the observation of Single-Event Upsets (SEU) and Total Ionizing Dose (TID) effect on a large number of stacked 64 Mbit Dynamic Random Access Memories (DRAM). As a result, the actual SEU rates could be calculated, and the capabilities of two types of on-the-fly Error Detection and Correction (EDAC) mechanisms were confirmed. This paper presents the results of the space experiment of SSR, focusing especially on SEU analysis

Electrical Characterization of 256 Mbit DRAM with Carbon-Implanted Drain

In this paper, we report a carbon-implanted drain on the contact to bitline per cell transistor investigated for 0.14 μm dynamic random access memory (DRAM) generation. It is found that an n-metal oxide semiconductor field effect transistor (n-MOSFET) with a carbon-implanted drain can promote a 7% improvement of production yield of a 256 Mbit DRAM. This technique exhibits excellent electrical properties such as threshold voltage, drive current, and bit contact resistance. This indicates that the presence of carbon suppresses transient enhanced diffusion and dislocation formation generated by other implant species.

Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor

We have compared the capacitances of a conventional stacked capacitor and hemispherical-grained silicon (HSG-Si), in which the seeding method was applied to storage electrode of 64 Mbit dynamic random access memory (DRAM) through Si 2H 6-molecule irradiation and annealing for HSG-Si formation. Also, we considered the variation of the HSG-Si thickness due to the phosphorus concentration of storage poly-silicon in process condition and the effect of its thickness on the cell capacitance and failure occurrence, etc. We investigated the effect of the deposition temperature of amorphous poly-silicon on the HSG-Si formation. As a result, the optimum process conditions of the phosphorus concentration, the deposition temperature of storage poly-silicon and the HSG thickness in HSG formation are 3.5–4.5×10 19 atoms/cm 3, 530°C and 450 Å, respectively. It is found that the limit thickness of dielectric film of 64 Mbit DRAM capacitor according to the optimized process condition is 65 Å.

Electron beam writing methods of x-ray masks for eliminating thermal image placement errors

In this article we describe electron beam writing methods to suppress image placement errors due to the thermal distortion and drift of x-ray masks. Parts of device patterns are written outside of the writing area of a mask before the device pattern writing step to stabilize the temperature of the mask (preparatory writing method). The seesaw writing method, which divides a pattern into many slit parts that are written reciprocally, is used to compensate for the nonuniformity of the heating rate of the mask according to the mask’s position on the stage. The absorber fiducial mark is formed on the mask instead of the cassette or the stage to prevent the drift of the mask, and furthermore, to reduce mask-to-mask overlay errors. The writing is performed by referring to the absorber coordination marks on the mask after the registrations of the marks are measured with an image placement (IP) measurement system (mark-on-the-mask method). The effectiveness of these methods is evaluated through the fabrication of a full-chip mask of a 64 Mbit dynamic random access memory, and an IP accuracy close to 20 nm is obtained.

Profiling of collimated swift ion microbeam using 16 M bit DRAM

High-energy heavy-ion microbeams are useful for studying single-event phenomena(SEP) in semiconductor devices. However, current SEP research is concentrating on higher energies provided by cyclotrons. Focusing such high-energy beams is extremely difficult so we have taken the approach of using microcollimator to form a highly collimated beam which can then be positioned accurately on the device under test. In order to measure the beam profiles produced by such a system, we have employed a 16 Mbit DRAM (dynamic random access memory) to measure both the occurrence of a single-event upset and its spatial location. Using the DRAM method, 150 MeV 40Ar 8+ beams collimated to 100 μm have been characterized. The results indicate that high integrated memory devices can replace a position-sensitive detector (PSD) and provide an even higher spatial resolution.

Leakage currents and conduction mechanisms of Ta 2O 5 layers on Si obtained by RF sputtering

The leakage current and the conduction mechanisms in Ta 2O 5 layers on silicon with thickness in the range of 20–80 nm, obtained by reactive sputtering of Ta in an Ar/O 2 mixture have been investigated. Some dielectric and electrical properties, important for the application of the layers as storage capacitors in high-density dynamic random access memories (DRAM) and as a gate dielectric in metal oxide silicon transistors (MOSTs) are also considered. The results show that for as-deposited layers the leakage currents are higher for samples obtained at higher deposition temperature. The effect of postdeposition oxygen annealing depends on the thickness of Ta 2O 5 layers. For thicker layers (40 nm), the leakage current after annealing increases and the effect is stronger for layers deposited at T s=493 K. It has been established that for thinner oxides (25 nm) the annealing strongly improves the leakage currents (the density of leakage current is 10 −7 A/cm 2 at applied fields of about 1 MV/cm, which is low enough to satisfy the demands of 64 and 256 Mbit DRAM). For as-deposited samples the conduction mechanism is Poole Frenkel. After annealing depending on the field strength, different types of conduction mechanisms occur: for electric fields in the range 0.8–1.3 MV/cm, the conduction mechanism is dominated by electrode limited Schottky emission and for higher fields (>1.5 MV/cm) it is bulk limited Poole Frenkel emission. The results are discussed in terms of bulk traps in the initial Ta 2O 5 and their modification after oxygen annealing.

Effects of Denudation Anneal of Silicon Wafer on the Characteristics of Ultra Large-Scale Integration Devices

The effectiveness of denudation annealing at high temperatures on the characteristics of ultra large-scale integration (ULSI) devices has been studied. The secondary-ion mass spectroscopy (SIMS) profile showed that the oxygen atoms near the wafer surface diffuse out during the denudation anneal and the amount of outdiffused oxygen atoms increases with the increase of denudation annealing temperature. The depth of the defect-free zone (DFZ) at the surface region, the breakdown property of the thin gate oxide of 7 nm thickness and the leakage current of PN junction diodes were greatly improved following by the denudation annealing process at a high temperature. It is found that the refresh properties of a 256 Mbit dynamic random-access memory (256 M-DRAMs) were closely related to the depth of the DFZ at the device surface and were improved by the denudation annealing. Therefore, denudation annealing at high temperatures is effective for the fabrication of reliable quarter-micron level DRAM devices.

Electronic structure of oxygen vacancy in Ta2O5

Ta 2 O 5 is a potential material for high dielectric constant insulators. The leakage current, however, should be reduced for application to 256 megabit dynamic random access memory. A state in the band gap induced by the oxygen vacancy is considered to lead to the leakage current. Ta2O5 was investigated theoretically in order to determine the effect of the oxygen vacancy. The calculated state originating from the oxygen vacancy is deeper than the experimentally obtained value. The strongly distorted local structure around the oxygen vacancy may give a shallow energy level, because the energy level of the vacancy state is shallower before structure optimization than after it.

A Fast Eliminating System of Narrow Electron-Beam Exposure-Figures for Improving Pattern Accuracy

We have developed a system for fast elimination of narrow electron-beam (EB) exposure-figures, which degrade pattern accuracy when using a variable shaped writing scheme. In order to reduce the processing time, a hierarchical and a distributed processing method have been developed. In addition, two kinds of narrow-figure elimination methods have been evaluated for further reduction of the processing time: a whole figure-merge method and a pinpoint figure-merge method. It was found that both methods must be selectively used because the best method strongly depends on the total amount of initial narrow figures in input data. The developed system has been applied to EB exposure data for 5× reticles of a 256 Mbit dynamic random access memory (DRAM). The pinpoint figure-merge method was used because its processing speed was 1.5 times higher than the other method for this case. The narrow-figure elimination has been completed successfully in a practical time; it was 2.8 hours for 4 critical layers of a 256 Mbit DRAM.

SIMS depth profiling and direct ion imaging of a 16-megabit DRAM

The use of secondary ion mass spectrometry (SIMS) has long been established as a powerful tool forthe analysis of microelectronic devices. However, as newer fabrication technologies emerge, and device dimensions shrink, increasing demands are placed upon the SIMS analyst.The present work illustrates how the depth profiling and direct ion imaging capabilities of a Cameca ims 4f SIMS can be exploited to determine the structure and dopant chemistry of a state-of-the-art16 megabit DRAM (dynamic random access memory) device. The optical micrograph shown in Fig. 1 is an overview of a portion of the sense amplifiers located between two array blocks. In the centre of this area, p-type devices sitting in an n-well, surrounded on either side by n-type devices, all in a p-type substrate can be observed. The object of the study was to determine if a low concentration p-type implant is present below the n-type devices.

Ultrathin Silicon Nitride Films Fabricated by Single‐Wafer Processing Using an SiH2Cl2 ‐ NH 3 ‐ H 2 System and In Situ H 2 Cleaning

We demonstrated the formation technique of highly reliable ultrathin oxidized silicon nitride film (34 Å in oxide equivalent thickness) on three‐dimensional cylindrical stacked capacitor cells. In situ cleaning and low‐pressure chemical vapor deposition of silicon nitride using and gases were successively carried out in a reactor, which can accommodate an 8 in. silicon wafer. The conduction current through the film was suppressed and the time‐to‐breakdown was substantially improved by the complete elimination of the bottom oxide. The intrinsic lifetime of the cylindrical stacked capacitors, which was comparable to that of the conventional stacked capacitors, was estimated to be long enough for use in 256 Mbit dynamic random access memory (DRAM). This result has revealed that the present single‐wafer process is very effective and practical for the three‐dimensional capacitor formation of the next generation DRAMs.

Electrical breakdown induced by silicon nitride roughness in thin oxide–nitride–oxide films

The time-dependent dielectric breakdown (TDDB) characteristics of thin oxide–nitride–oxide (ONO) films containing 4 nm of Si3N4 were found to be exclusively determined by statistical thickness fluctuations of the Si3N4 layer. A two-parameter statistical model describes this roughness and explains experimental TDDB data. A simple growth model combined with the statistical model reduces the number of parameters to one. It is consistent with TDDB data and is in quantitative agreement with transmission electron microscopy and x-ray photoelectron spectroscopy data and is able to explain the origin of the roughness. On an ONO with a 4 nm Si3N4 layer and an area of 8 cm2—corresponding to the total storage area of a 256 Mbit dynamic random access memory—the thinnest point in the Si3N4 can be expected to be below 10 Å. So eliminating the Si3N4 roughness would bring a drastic improvement in reliability.

Hemispherical grained Si formation on in-situ phosphorus doped amorphous-Si electrode for 256 Mb DRAM's capacitor

The cylindrical capacitor structure with hemispherical grained-Si (HSG-Si) described here reliably achieves a cell capacitance of 30 fF in a 0.4 /spl mu/m-high storage electrode with a cell area of a 0.72 /spl mu/m/sup 2/ for 256 Mbit dynamic random access memory. An HSG-Si formation technology using Si/sub 2/H/sub 6/-molecule irradiation and annealing enables control of the grain density and grain size of HSG-Si fabricated selectively on the whole surface of phosphorus-doped amorphous Si cylindrical electrodes. >

Al-Reflow Process with a “Cap-Clamp” for Sub-Micron Contact Holes

The use of “cap-clamp” has been demonstrated for extending the process margin of Al-reflow process. To evaluate the process window of Al-reflow with and without the “cap-clamp”, two major factors of in-situ annealing temperature and time were varied between 500-560° C and 40-90 seconds, respectively. Sub-micron contact holes were completely filled by heating wafers at 500° C or higher temperatures by adopting the “cap-clamp” to the conventional conduction heating system. The effect of the “cap-clamp” comes from the improved heating efficiency of the wafer by introducing hot Ar gas into the inner space of “cap-clamp”, resulting in faster ramp-up as well as more effective heating of the front-side of the wafer. Al-reflow with the “cap-clamp” gives wider process window than that of the conventional heating method and realizes the contact planarization of 256 Mbit dynamic random access memory (DRAM) and beyond.

The Application of Deep UV Phase Shifted-Single Layer Halftone Reticles to 256 Mbit Dynamic Random Access Memory Cell Patterns

We have applied deep UV (DUV) halftone reticles, with a single layer absorptive shifter consisting of silicon nitride, to 256 Mbit dynamic random access memory (DRAM) critical levels, and have evaluated the resolution in those cell patterns. For the periodic line levels, halftone reticles were combined with off-axis illumination (OAI) techniques. Resolution capabilities were characterized not only with stepper exposures but also with direct aerial image measurement. For hole levels such the Storage Node and Bitline Contact, halftone reticles offered clear improvement with standard illumination as compared to conventional reticles. For line levels such the Isolation, Wordline and Bitline, dramatic improvement was obtained with the combination of halftone reticles and off-axis illumination.

Application of Proximity Effect Correction Using Pattern-Area Density to Patterning on a Heavy-Metal Substrate and the Cell-Projection Exposure

Proximity effect correction for electron beam (EB) direct writing is studied in this paper. An iterative calculation of exposure-dose modulation by equalizing the deposited energy of all figures requires an extremely long calculation time, especially in the case of high EB acceleration voltage. Therefore it is not practical for the correction of LSI. The correction method using pattern-area density, however, could realize the high-speed proximity effect correction. In this paper, this method is first investigated from the standpoint of the correction accuracy. Next, the applicability of this method to two critical cases is examined. One is the patterning on a heavy-metal substrate, on which backscattering yield of electrons is high. The other is the application to the cell-projection exposure, in which it is impossible to modulate exposure dose inside the cell. Lastly, the calculation time of the proximity effect correction is evaluated for 64 Mbit dynamic random access memories (MbDRAMs).

Dielectric Properties of (BaxSr1-x)TiO3 Thin Films Prepared by RF Sputtering for Dynamic Random Access Memory Application

Dielectric properties of (Ba0.5Sr0.5)TiO3 and (Ba0.75Sr0.25)TiO3 thin films have been investigated, focusing on the effects of film structure and Ba/Sr compositions on the dielectric properties. Dielectric constant of the films increased with increasing grain size and with improvement in film crystallinity. For the 50-nm-thick films deposited at 660° C, the dielectric constant of 400 for the (Ba0.5Sr0.5)TiO3 film is larger than that of 320 for the (Ba0.75Sr0.25)TiO3 film. This indicated that dielectric constant is affected by the ratio of Ba/Sr composition. Leakage current density of less than 1×10-7 A/cm2 at 1 V and SiO2 equivalent thickness of 0.38 nm are measured at 120° C for 660° C-deposited (Ba0.5Sr0.5)TiO3 film of 30 nm in thickness. The (Ba0.5Sr0.5)TiO3 film has the possibility for application to generations beyond 256 Mbit dynamic random access memories.

The Effect of the Crystal Grown‐in Defects on the Pause Tail Characteristics of Megabit Dynamic Random Access Memory Devices

The effect of the crystal grown‐in defects on the pause tail characteristics of megabit dynamic random access memory devices was investigated. By comparing the performance of the devices fabricated on epitaxial silicon wafers with those fabricated on polished Czochralski silicon wafers, it was found that the refresh time of the memory devices fabricated on a polished silicon wafer is strongly affected by the crystal grown‐in defects. Based upon the present results, the refresh time failure of the memory devices could be attributed to several types of crystal defects which include the D‐defects produced as a result of vacancy aggregation during crystal growth and those associated with oxygen precipitation.