Simulator MEDICI Research Articles

A new two-dimensional analytical subthreshold behavior model for short-channel tri-material gate-stack SOI MOSFET’s

On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the short-channel tri-material gate-stack SOI MOSFET’s is developed. The model is verified by its good agreement with the numerical simulation of the device simulator MEDICI. The model not only offers physical insight into the device physics but also provides guidance for the basic design of the device.

습식 산화를 이용한 원형 트렌치 게이트 IGBT에 관한 연구

The conventional IGBT has two problems to make the device taking high performance. The one is high on state voltage drop associated with JFET region, the other is low breakdown voltage associated with concentrating the electric field on the junction of between p base and n drift. This paper is about the structure to effectively improve both the lower on state voltage drop and the higher breakdown voltage than the conventional IGBT. For the fabrication of the circular trench IGBT with the circular trench layer, it is necessary to perform the only one wet oxidation step for the circular trench layer. Analysis on both the on state voltage drop and the breakdown voltage show the improved values compared to the conventional IGBT structure. Because the circular trench layer disperses electric field from the junction of between p base and n drift to circular trench, the breakdown voltage increase. The on state voltage drop decrease due to reduction of JFET region and direction changed of current path which pass through reversed layer channel. The electrical characteristics were studied by MEDICI simulation results.

A New Analytical Subthreshold Behavior Model for Single-Halo, Dual-Material Gate Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistor

On the basis of the exact solution of the two-dimensional Poisson equation, a new analytical subthreshold behavior model consisting of the two-dimensional potential, threshold voltage, and subthreshold current for the single-halo, dual-material gate (SHDMG) silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is developed. The model is verified by the good agreement with a numerical simulation using the device simulator MEDICI. The model not only offers a physical insight into device physics but is also an efficient device model for the circuit simulation.

Optimization of on-State and Switching Performances for 15–20-kV 4H-SiC IGBTs

The 4H-SiC p-channel IGBTs designed to block 15 and 20 kV are optimized for minimum loss (on-state plus switching power) by adjusting the parameters of the JFET region, drift layer, and buffer layer, using 2-D MEDICI simulations. Switching loss exhibits a strong dependence on buffer layer thickness, doping, and lifetime due to their influence on the current tail. In contrast, drift layer lifetime has little effect on the crossover frequency at which the MOSFET and IGBT have equal loss.

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P+ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S21| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.

Physical Mechanism of p-i-n-Diode-Based Photonic Crystal Silicon Electrooptic Modulators for Gigahertz Operation

In this paper, the physical mechanism governing the optical modulation in a p-i-n-diode-embedded photonic crystal (PC) silicon Mach-Zehnder interferometer modulator is examined. Optical simulations have been performed to study how the slow group velocity of the photonic crystal waveguides enables a significant reduction of device size. The theoretical speed limitation in a PC-based silicon modulator is also explored. The 2-D semiconductor device simulator MEDICI has been employed to analyze the transient behavior of the p-i-n-diode-embedded silicon modulator. Electrical simulations have revealed a significant improvement in modulation speed upon the enhancement of current density in a downscaled PC device. High-speed optical modulation at 1 Gmiddots-1 has been experimentally demonstrated. The performance degradation in optical modulation at the low-frequency operation region attributed to the thermooptic effect is identified and discussed. Simulations have also revealed that the modulation speed of our device can be improved up to 10 GHz by further reducing the device dimensions with little penalty of the increased optical loss.

On-Resistance Degradations for Different Stress Conditions in High-Voltage pLEDMOS Transistor With Thick Gate Oxide

The different on-resistance degradations of the p-type lateral extended drain MOS (pLEDMOS) transistor with thick gate oxide for different hot carrier stress conditions have been experimentally investigated for the first time. The difference results from the interface trap generation and the hot electron injection and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor, which has been analyzed in detail using the MEDICI simulator.

Evaluation of MOSFETs with crystalline high-k gate-dielectrics: device simulation and experimental data

The evaluation of the world’s first MOSFETs with epitaxially-grown rare-earth high-k gate dielectrics is the main issue of this work. Electrical device characterization has been performed on MOSFETs with high-k gate oxides as well as their reference counterparts with silicon dioxide gate dielectric. In addition, by means of technology simulation with TSUPREM4, models of these devices are established. Current-voltage characteristics and parameter extraction on the simulated structures is conducted with the device simulator MEDICI. Measured and simulated device characteristics are presented and the impact of interface state and fixed charge densities is discussed. Device parameters of high-k devices fabricated with standard poly-silicon gate and replacement metal gate process are compared.

Root Cause of Charge Loss in a Nitride-Based Localized Trapping Memory Cell

Data retention loss mechanisms in nitride-based localized trapping memory devices are investigated with various electrical measurements and Medici simulations. First, the effect of program and erase cycles on device behavior is determined in terms of bottom oxide degradation and nitride charge profile evolution. Even if a strong degradation of the interface is observed, there is no important impact of this degradation on the cell behavior. However, the nitride charge profile evolves with cycling and leads to a three-pole electron-hole-electron profile over the channel region. Second, the interface trap annealing, the tunneling through the bottom oxide, and the lateral redistribution are studied in order to determine which mechanism plays the main role in the threshold voltage shift after cycling. The retention performance is dominated by a lateral redistribution of charges in the nitride layer.

Effect of Channel Length in LDMOSFET on the Switching Characteristic of CMOS Inverter

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

Modeling of Surrounding Gate MOSFETs With Bulk Trap States

We report a simple analytical model for surrounding gate MOSFETs including bulk traps. Based on the depletion approximation and the assumption that bulk traps are uniformly distributed inside the bandgap, we solved Poisson's equation in cylindrical coordinates and derived the general solution of potential distribution. Extraction of threshold voltage and subthreshold slope were conducted. The analytical solution yields good agreement with MEDICI simulations confirming the model. The model predicts a linear threshold voltage drop, depending on the trap density, as the diameter of the device decreases when the channel is fully depleted

Current gain of SiGe HBTs under high base doping concentrations

As high doping concentrations and high Ge contents are implemented in the base regions of SiGe heterojunction bipolar transistors (HBTs) to improve device performance, neutral base recombination (NBR) is also simultaneously enhanced. The enhanced NBR can severely degrade the current gain values of SiGe HBTs and thus needs to be carefully considered in device design. In this paper, a new analytical expression for the current gain of SiGe HBTs is derived to include the NBR component in the base current. The new current gain expression indicates that the maximum achievable current gain of SiGe HBTs is limited by the NBR and can be realized via optimization of the Ge profile. The analyses of the current gain of SiGe HBTs employing high base doping concentrations and high Ge contents are verified with MEDICI simulations.

Enhanced Band-to-Band-Tunneling-Induced Hot-Electron Injection in p-Channel Flash by Band-gap Offset Modification

A novel p-channel flash device with a SiGe layer is proposed, which is based on the analysis made with the simulator MEDICI, to enhance the band-to-band-tunneling current and improve the programming speed. The programming biases of the p-channel flash device can be reduced with an equal programming speed. Simulation results show that more than one hundred times enhancement in the programming speed or 35% reduction of the drain voltage can be achieved in the proposed p-channel flash device with a 40% Ge content in the surface SiGe layer. In addition, a Si-cap layer is inserted between the SiGe and the tunneling oxide to obtain a high-quality interface and to optimize the cell structure

Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology

In this paper, we show that when single gate SOI MOSFETs are biased at a particular ideal back gate voltage, the front and back channels can be turned ON and OFF simultaneously using the front gate voltage, thereby enhancing the current drive of the device. It is shown by analytical models as well as 2-D numerical simulation that both maximum transconductance and minimum subthreshold slope are obtained for this ideal back gate bias. Subsequently, n-channel and p-channel MOSFETs are designed for a conventional SOI CMOS process, where both the front and back channels of these devices turn ON and OFF simultaneously resulting in enhanced current drive and superior performance. The design has been carried out with the help of analytical formulation and verified using the 2-D Device Simulator MEDICI.

Electrical Characteristics of CMOS Circuit Due to Channel Region Parameters in LDMOSFET

The electrical characteristics of CMOS inverter with LDMOSFET are studied for high power and digital circuit application by using two dimensional MEDICI simulator. The simulation is done in terms of voltage transfer characteristic and on-off switching properties of CMOS inverter with variation of channel length and channel doping levels. The channel which surrounds a junction-type source in LDMOSFET is considered to be an important parameter to decide a circuit operation of CMOS inverter. The digital logic levels of input voltage show to increase with increase of n-channel length and doping levels while the logic output levels show to the almost constant.

DESIGN, MODELING, TESTING, AND SPICE PARAMETER EXTRACTION OF DIMOS TRANSISTOR IN 4H-SILICON CARBIDE

In this paper, an analytical model for a vertical double implanted metal-oxide semiconductor (DIMOS) transistor structure in 4H-Silicon Carbide ( SiC ) is presented. Simulation for transport characteristics of the SiC MOSFET with the exact device geometry is carried out using the commercial device simulator MEDICI. A rigorous experimental testing and characterization is done on a 4H- SiC DIMOS transistor test device. SPICE parameters are extracted from the measurements, and a SPICE model for the DIMOS transistor has been developed. The presented work is a part of team efforts of material, device, and power electronics researchers at the University of Tennessee and Oak Ridge National Laboratory.

Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si1?xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including: 1) the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2) the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3) better transistor matching; and 4) flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.

Numerical study on the scaling of a-Si:H thin film transistors

In this article we discuss the impact of channel length scaling on the above threshold current characteristics of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs). MEDICI simulation results of the interface surface potential show a lowering of the potential barrier for shorter channel lengths. This suggests a decrease in threshold voltage and increase in subthreshold slope with drain voltage particularly in submicron channel lengths, causing a nonsaturating output current. Simulation results of the above threshold current-voltage characteristics for short channel TFTs corroborate with measurement data of fabricated devices.

A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI (Silicon On Insulator) high voltage device with Step Unmovable Surface Charges (SUSC) of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson’s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF (REduce SURface Field) condition of the SOI device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3μm-thick top Si layer, 2μm-thick buried oxide layer and 70μm-length drift region using a linear doping profile of unmovable buried oxide charges.

SiCGe/SiC heterojunction and its MEDICI simulation of optoelectronic characteristics

Optoelectronic characteristics of the SiC1−xGex /SiC heterojunction photodiode are simulated using MEDICI after the theoretical investigation of key properties for SiC1−xGex. The calculations show that SiC1−xGex /SiC with x=0.3 may have a small lattice mismatch with 3C-SiC and a good response to the visible light and the near infrared light. The response spectrum of the SiC1−xGex /SiC heterojunction photodiode, which consists of a p-type SiC1−xGex absorption layer with a doping concentration of 1×1015cm−3, a thickness of 1.6μm and x=0.3, has a peak of 250mA/W at 0.52μm and the peak can even reach 102mA/W at 0.7μm.