Measurement Dead Time Research Articles

A modified decaying source method for dead time measurement with non-negligible background counts

This study aims to propose a modified decaying source method for dead time measurement with non-negligible background counts. A radiation portal monitor (RPM) system with 173×28.4×6.4 cm3 sized PVT scintillation detectors was used for the experiment. For each source, various activities were measured to evaluate counting losses due to the dead time, and three types of sources were considered to validate the energy dependency of the dead time. The results showed that the evaluated true count rate based on the nonparalyzable dead time model is in good agreement with the experimental data and the dead time increases when the energy of the incident radiation decreases. The proposed method is expected to be used for dead time measurement of radiation detection systems with non-negligible background counts.

Random-telegraph noise mitigation and qubit decoherence in solid-state experiments

We investigate the recently proposed theoretical models and algorithms in Song et al. [1] for mitigating decoherence in solid-state qubit systems, where qubits are affected by charge (random telegraph) noises. The model includes a setup of a logical qubit (data qubit) and a spectator qubit, where the latter is used as a probe of the noise. The probe results can be used in correcting the phase error in order to improve the decoherence of the data qubit. In this work, we apply the proposed model with parameters extracted from recent solid-state qubit experiments. We extract parameters such as the noise switching rates, the qubit sensitivities to noise, and the measurement dead time. Using these parameters, we then numerically simulate the data qubit’s phase and the qubit decoherence. We also show that the proposed phase-correction technique using Bayesian estimation can improve the data qubit decoherence significantly.

Analysis of Statistical Uncertainty of Optical Frequency Measurement Due to Measurement Dead Time of Hydrogen Maser

Analysis of Statistical Uncertainty of Optical Frequency Measurement Due to Measurement Dead Time of Hydrogen Maser

A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme

A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.

A new dead-time determination method for gamma-ray detectors using attenuation law

This study presents a new dead-time measurement method using the gamma attenuation law and generalized dead-time models for nuclear gamma-ray detectors. The dead-time of the NaI(Tl) detection system was obtained to validate the new dead-time determination method using very thin lead and polyethylene absorbers. Non-paralyzing dead-time was found to be 8.39 μs, and paralyzing dead-time was found to be 8.35 μs using lead absorber for NaI(Tl) scintillator detection system. These dead-time values are consistent with the previously reported dead-time values for scintillator detection systems. The gamma build-up factor's contribution to the dead-time was neglected because a very thin material was used.

A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

Taking the system clock as the reference, a ring-oscillator based Vernier-type time stamping method is proposed for the implementation of time-to-digital converters (TDCs) on field programmable gate array (FPGA). A module with this method called time-marker is implemented on a Xilinx Kintex-7 FPGA and tested with 43 ps time resolution and less than 50 ns measurement dead time. To illustrate this time-marker can be used as the building block for TDC construction to provide high time measurement performance with low resource consumption, a multi-mode TDC using eight time-markers is implemented with performance evaluation. The TDC has three flexible configuration modes for performance enhancements in three aspects. In the multi-channel mode, it becomes eight independent TDC channels with average 34 ps time interval RMS precision and 50 ns measurement dead time; in the high-precision mode, it is one TDC channel with 14 ps RMS precision and 50 ns measurement dead time; and in the high-throughput mode, it is one TDC channel with 33 ps RMS precision and 6.25 ns measurement dead time. In addition, the temperature dependence of the performance is evaluated.

Compact chip-scale guided cold atom gyrometers for inertial navigation: Enabling technologies and design study

This work reviews the topic of rotation sensing with compact cold atom interferometers. A representative set of compact free-falling cold atom gyroscopes is considered because, in different respects, they establish a rotation-measurement reference for cold guided-atom technologies. This review first discusses enabling technologies relevant to a set of key functional building blocks of an atom chip-based compact inertial sensor with cold guided atoms. These functionalities concern the accurate and reproducible positioning of atoms to initiate a measurement cycle, the coherent momentum transfer to the atom wave packets, the suppression of propagation-induced decoherence due to potential roughness, on-chip detection, and vacuum dynamics because of its impact on sensor stability, which is due to the measurement dead time. Based on the existing enabling technologies, the design of an atom chip gyroscope with guided atoms is formalized using a design case that treats design elements such as guiding, fabrication, scale factor, rotation-rate sensitivity, spectral response, important noise sources, and sensor stability.

A 3.0-ps rms Precision 277-MSamples/s Throughput Time-to-Digital Converter Using Multi-Edge Encoding Scheme in a Kintex-7 FPGA

In a field-programmable gate array (FPGA)-based time-to-digital converter (TDC), the hit signal to be measured launches out a segment of the clock-like signal propagating along the tapped delay line (TDL). If every edge of the clock-like signal in the TDL status is identified by the encoder, parallel multiple measurements can be achieved to improve the TDC time precision. In this article, we propose a bubble-proof multi-edge encoding scheme by hardware in pipeline fashion, which can achieve 277-MSamples/s measurement throughput on a Kintex-7 FPGA. Based on the encoding scheme, TDCs with 1-, 2-, 4-, 6-, and 8-edge multiple measurements are sequentially implemented. The corresponding average rms precisions measuring time intervals from 0 to 50 ns are evaluated as 8.2, 4.8, 3.5, 3.1, and 3.0 ps, respectively. The test results confirm that the proposed TDC with a multi-edge encoding scheme can effectively improve TDC time precision without adding TDC measurement dead time. Its resource-saving feature also makes it feasible for multi-channel TDC integration.

A time-driven FPGA-based fast nuclear charge digitization method

Abstract Without the need of high-speed analog-to-digital converters (ADCs), the method of translating the shape of nuclear pulses into a time width for charge measurement provides the possibility of multi-channel system implementation with commercialized discrete components. In this paper, we propose such a circuit scheme based on field programmable gate array (FPGA) to realize nuclear charge digitization. Compared with other charge digitizing methods using discrete components, the proposed scheme has a shorter measurement dead time and high measurement performance. Since some logic units of the FPGA are developed to replace discrete analog devices, only one additional analog amplifier for each channel is required outside of the FPGA, which makes the circuit scheme compact and feasible for the implementation of multi-channel systems. Combining with a positron emission tomography (PET) detector module that consists of LYSO crystals coupled with a SiPM array for 22Na coincidence measurement, the circuit can achieve the energy resolution of 12.3% with a typical measurement dead time of 500 ns. Using a reference detector with 164.7 ps time resolution, the coincidence time resolution of the two detectors is evaluated as 367.1 ps, which means the proposed circuit also has an acceptable time performance for some applications.

Implementation of 5.3 ps RMS precision and 350 M samples/second throughput time-to-digital converters with event sampling architecture in a Kintex-7 FPGA

Unlike the conventional field programmable gate array (FPGA) based time-to-digital converter (TDC) with clock sampling architecture, the TDC with event sampling architecture implemented in this paper propagates the system clock signal along the tapped-delay line (TDL) and the TDL status is sampled by a hit signal for time interpolation. Since there are several “1–0” and “0–1” transitions in the sampled TDL status, the TDC naturally realizes multiple measurements in parallel without increasing the resource consumption and the measurement dead time. Using a Xilinx Kintex-7 FPGA, we increase the number of equivalent TDC bins approximately to twice the number of physical delay cells in the TDL, which means the TDC resolution is about twice as good as the original. The average RMS precision is measured as 5.3 ps with two identical TDC channels measuring the time intervals in the range 0 to 20 ns. The proposed encoding scheme is so efficient that the TDC measurement throughput can reach 350 M samples per second. The test results show that the event sampling architecture is effective in FPGA as well. The performance that can be achieved is comparable with the performance of their counterparts that use the clock sampling architecture.

An FPGA-Based Fast Linear Discharge Readout Scheme Enabling Simultaneous Time and Energy Measurements for TOF-PET Detectors

The readout electronics in time-of-flight positron emission tomography (TOF-PET) detector modules conventionally contain a separate timing circuit and a separate energy measurement circuit. For channel-by-channel readouts, the front-end electronics will be unacceptably large and must rely on application specific integrated circuit (ASIC) chips. In this paper, we present a novel field programmable gate array (FPGA)-based readout scheme that unifies the time and energy measurements with only one analog amplifier per channel in addition to the FPGA. By constructing a simple and effective fast linear discharge circuit, one time-to-digital converter (TDC) per channel can implement time and energy readouts simultaneously with a short measurement dead time. To evaluate the performance of the new approach, a 16-channel PET detector module consisting of LYSO crystals coupled with a silicon photomultiplier (SiPM) array was constructed connecting to the readout electronics. Using a reference detector with a 164.7-ps time resolution to perform 22Na coincidence measurements, the average energy, and time resolution among 16 channels were measured as 12.44% and 372.6 ps, respectively. The typical measurement dead time is approximately 300 ns. The test results show the simplicity and feasibility of the proposed readout scheme, which is particularly useful for laboratory instrumentation.

Simple and ultrafast resonance frequency and dissipation shift measurements using a fixed frequency drive

A new method for determination of resonance frequency and dissipation of a mechanical oscillator is presented. Analytical expressions derived using the Butterworth-Van Dyke equivalent electrical circuit allow the determination of resonance frequency and dissipation directly from each impedance datapoint acquired at a fixed amplitude and frequency of drive, with no need for numerical fitting or measurement dead time unlike the conventional impedance or ring-down analysis methods. This enables an ultrahigh time resolution and superior noise performance with relatively simple instrumentation. Quantitative validations were carried out successfully against the impedance analysis method for inertial and viscous loading experiments on a 14.3 MHz quartz crystal resonator (QCR). Resonance frequency shifts associated with the transient processes of quick needle touches on a thiol self-assembled-monolayer functionalised QCR in liquid were measured with a time resolution of 112 μs, which is nearly two orders of magnitude better than the fastest reported quartz crystal microbalance. This simple and fast fixed frequency drive (FFD) based method for determination of resonance frequency and dissipation is potentially more easily multiplexable and implementable on a single silicon chip delivering economies of scale.

Advanced readout methods for superheated emulsion detectors.

Superheated emulsions develop visible vapor bubbles when exposed to ionizing radiation. They consist in droplets of a metastable liquid, emulsified in an inert matrix. The formation of a bubble cavity is accompanied by sound waves. Evaporated bubbles also exhibit a lower refractive index, compared to the inert gel matrix. These two physical phenomena have been exploited to count the number of evaporated bubbles and thus measure the interacting radiation flux. Systems based on piezoelectric transducers have been traditionally used to acquire the acoustic (pressure) signals generated by bubble evaporation. Such systems can operate at ambient noise levels exceeding 100 dB; however, they are affected by a significant dead time (>10 ms). An optical readout technique relying on the scattering of light by neutron-induced bubbles has been recently improved in order to minimize measurement dead time and ambient noise sensitivity. Beams of infra-red light from light-emitting diode (LED) sources cross the active area of the detector and are deflected by evaporated bubbles. The scattered light correlates with bubble density. Planar photodiodes are affixed along the detector length in optimized positions, allowing the detection of scattered light from the bubbles and minimizing the detection of direct light from the LEDs. A low-noise signal-conditioning stage has been designed and realized to amplify the current induced in the photodiodes by scattered light and to subtract the background signal due to intrinsic scattering within the detector matrix. The proposed amplification architecture maximizes the measurement signal-to-noise ratio, yielding a readout uncertainty of 6% (±1 SD), with 1000 evaporated bubbles in a detector active volume of 150 ml (6 cm detector diameter). In this work, we prove that the intensity of scattered light also relates to the bubble size, which can be controlled by applying an external pressure to the detector emulsion. This effect can be exploited during the readout procedure to minimize shadowing effects between bubbles, which become severe when the latter are several thousands. The detector we used in this work is based on superheated C-318 (octafluorocyclobutane), emulsified in 100 μm ± 10% (1 SD) diameter drops in an inert matrix of approximately 150 ml. The detector was operated at room temperature and ambient pressure.

DEAD TIME MEASUREMENT BY TWO-SOURCE METHOD – OPTIMIZATION OF MEASUREMENT TIME DIVISION

The article presents the analysis of the dead time measurement using two sources for a non-paralyzable detector. It determined the optimum division of count rate measurement time between both source measurement and a single source one. Results of the work can be used to optimize dead time measurement for systems which count photons or particles.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9ps time-interval RMS precision, 16 TDC channels with 6.9ps RMS precision, or 8 TDC channels with 5.8ps RMS precision. All TDCs have a 380M Samples/second measurement throughput and a 2.63ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA

Field programmable gate arrays (FPGAs) manufactured with more advanced processing technology have faster carry chains and smaller delay elements, which are favorable for the design of tapped delay line (TDL)-style time-to-digital converters (TDCs) in FPGA. However, new challenges are posed in using them to implement TDCs with a high time precision. In this paper, we propose a bin realignment method and a dual-sampling method for TDC implementation in a Xilinx UltraScale FPGA. The former realigns the disordered time delay taps so that the TDC precision can approach the limit of its delay granularity, while the latter doubles the number of taps in the delay line so that the TDC precision beyond the cell delay limitation can be expected. Two TDC channels were implemented in a Kintex UltraScale FPGA, and the effectiveness of the new methods was evaluated. For fixed time intervals in the range from 0 to 440 ns, the average RMS precision measured by the two TDC channels reaches 5.8 ps using the bin realignment, and it further improves to 3.9 ps by using the dual-sampling method. The time precision has a 5.6% variation in the measured temperature range. Every part of the TDC, including dual-sampling, encoding, and on-line calibration, could run at a 500 MHz clock frequency. The system measurement dead time is only 4 ns.

PMT overshoot study for the JUNO prototype detector**Supported by Strategic Priority Research Program A-JUNO, High Energy Physics Experiment and Detector R&D and National Natural Science Foundation of China

The quality of PMT signals is crucial for large-size and high-precision neutrino experiments, but most of these experiments are affected by the overshoot of PMT signals from the positive HV-single cable scheme. Overshoot affects the trigger, dead time and charge measurement from a detector. For the JUNO prototype detector, we have performed a detailed study and calculation on PMT signal overshoot to control the ratio of overshoot to signal amplitude to ∼1%, with no effect on other PMT parameters.

Oscillator metrology with software defined radio.

Analog electrical elements such as mixers, filters, transfer oscillators, isolating buffers, dividers, and even transmission lines contribute technical noise and unwanted environmental coupling in time and frequency measurements. Software defined radio (SDR) techniques replace many of these analog components with digital signal processing (DSP) on rapidly sampled signals. We demonstrate that, generically, commercially available multi-channel SDRs are capable of time and frequency metrology, outperforming purpose-built devices by as much as an order-of-magnitude. For example, for signals at 10 MHz and 6 GHz, we observe SDR time deviation noise floors of about 20 fs and 1 fs, respectively, in under 10 ms of averaging. Examining the other complex signal component, we find a relative amplitude measurement instability of 3 × 10(-7) at 5 MHz. We discuss the scalability of a SDR-based system for simultaneous measurement of many clocks. SDR's frequency agility allows for comparison of oscillators at widely different frequencies. We demonstrate a novel and extreme example with optical clock frequencies differing by many terahertz: using a femtosecond-laser frequency comb and SDR, we show femtosecond-level time comparisons of ultra-stable lasers with zero measurement dead-time.

TOT measurement implemented in FPGA TDC**Supported by National Natural Science Foundation of China (11079003, 10979003)

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.

GM counter deadtime dependence on applied voltage, operating temperature and fatigue

This paper utilized standard two-source method and the simple non-paralyzing model assumption to examine a GM counter's deadtime dependence on applied voltage, operating temperature, and fatigue. Both 60Co and 137Cs sources were used for deadtime measurements. The results gathered suggest the presence of three distinct regions of deadtime behavior. At low voltages, the deadtime decreases as the voltage increases (Region I) followed by a region of stable deadtime plateau (Region II) and finally a region of increasing deadtime with increasing voltage. Region II is the best region for operating with a minimum deadtime which is not sensitive to the applied voltage. Typical deadtime values for GM counters were between 100 and 300 μs; the deadtime values in Region II were within this range. The results examined in this study also indicate a strong temperature dependence of deadtime, with a correlation coefficient of 0.93. The GM counter deadtime for various fatigues (aging) were investigated for three fatigue levels with a correlation coefficient of 0.48. The experimental results confirm that deadtime increases as both temperature and fatigue increase. The fundamental nature of deadtime seems to be different for voltages lower than the stable deadtime plateau (Region II) and for voltages higher than the plateau.