Maximum Supply Voltage Research Articles

Technology-driven limits on runtime power management algorithms for multiprocessor systems-on-chip

Runtime power management is a critical technique for reducing the energy footprint of digital electronic devices and enabling sustainable computing, since it allows electronic devices to dynamically adapt their power and energy consumption to meet performance requirements. In this article, we consider the case of MultiProcessor Systems-on-Chip (MPSoC) implemented using multiple Voltage and Frequency Islands (VFIs) relying on fine-grained Dynamic Voltage and Frequency Scaling (DVFS) to reduce the system power dissipation. In particular, we present a framework to theoretically analyze the impact of three important technology-driven constraints; (i) reliability-driven upper limits on the maximum supply voltage; (ii) inductive noise-driven constraints on the maximum rate of change of voltage/frequency; and (iii) the impact of manufacturing process variations on the performance of DVFS control for multiple VFI MPSoCs. The proposed analysis is general, in the sense that it is not bound to a specific DVFS control algorithm, but instead focuses on theoretically bounding the performance that any DVFS controller can possibly achieve. Our experimental results on real and synthetic benchmarks show that in the presence of reliability- and temperature-driven constraints on the maximum frequency and maximum frequency increment, any DVFS control algorithm will lose up to 87% performance in terms of the number of steps required to reach a reference steady state. In addition, increasing process variations can lead to up to 60% of fabricated chips being unable to meet the specified DVFS control specifications, irrespective of the DVFS algorithm used. Nonetheless, we note that although conventional DVFS might become less effective with technology scaling, it will continue to play an important role in the context of emerging power management techniques, for example, for massively parallel multiprocessor systems where only a subset of cores can be turned on at any given point of time due to total power constraints.

Methods for optimizing the performance of directed acyclic graphs operating under strict energy constraints on multi-core architectures

The problem of energy-constrained performance optimization (as opposed to performance-constrained energy optimization) for parallel applications has garnered considerable attention in the area of sustainable computing. This paper surveys algorithms developed for effectively minimizing the degradation in schedule length that results from rescheduling a parallel program to multi-core systems under an energy budget. By utilizing dynamic voltage scaling and the structural properties of the directed acrylic graph (DAG) representing the parallel program, we embrace four static techniques in order to achieve this goal. These heuristics encompass procedures. The first is assigning to a set of tasks a maximum supply voltage followed by methodical voltage reductions, thereby geometrically “stretching” the schedule. The second is assigning to tasks a minimum supply voltage followed by judicious boosts in voltage, thereby “compressing” the schedule. In contrast with the second technique, the third method completely reschedules the DAG following each voltage adjustment. However, this technique largely follows the same procedure as the second method. The surveyed techniques effectively determine what nodes receive voltage adjustments by calculating and comparing each task's “Impact Factor”, a metric devised to assist in the intelligent allocation of resources. Calculating the “Impact Factor” of each task (node) involves examining the entire context of the DAG, a rather expensive process. In contrast with the three previous techniques, a fourth method relies only upon the local characteristics of the DAG and state of the schedule for determining a core's viability for supply voltage raise, severely reducing run-time complexity. Detailed simulation experiments demonstrate the effect of various task and processor parameters on the performance of the surveyed algorithms.

Threshold Voltage Dependence on Bias for FinFET using Analytical Potential Model

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

Characteristics of Break Arcs Driven by Transverse Magnetic Field in a DC High-Voltage Resistive Circuit

Break arcs are generated between pure silver electrical contacts in a DC high-voltage resistive circuit. The break arc is driven by the external magnetic field of a permanent magnet from horizontal direction of contacts. Electrical contacts are separated at constant opening speed at 75 mm/s. The maximum supply voltage is 300 V. The maximum circuit current when electrical contacts are closed is 20 A. The maximum output power of the supply is limited to 6.0 kW. The gap between the contacts and the magnet is defined as x. The gap is varied from 2.5 mm to 10.0 mm to change the magnetic flux density that affects the break arc. The break arc is observed with a high-speed camera. The effect of the magnetic field on the arc duration was examined. As a result, break arcs are successfully extinguished by the transverse magnetic field when the gap x is 2.5 mm. Then the length of the break arc just before lengthening of the break arc L and the Lorentz force that affects the break arc F are examined. The length L was almost constant for each gap x and independent of the circuit current I and the Lorentz force F. The break arc is driven by the magnetic field when the arc length reached a certain length that was determined by the strength of the magnetic flux density.

Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement

Increasingly significant power/ground (P/G) supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction, which requires stochastic analysis and optimization techniques. We represent the supply voltage degradation at a P/G node as a function of the supply currents and the effective resistance of a P/G supply network and propose an efficient stochastic system-level P/G supply voltage prediction method, which computes P/G supply network effective resistances in a random walk process. We further propose to reduce P/G supply voltage degradation via placement of supply current sources, and integrate P/G supply voltage degradation reduction with conventional placement objectives in an analytical placement framework. Our experimental results show that the proposed stochastic P/G supply network prediction method achieves 10x-100x speedup compared with traditional SPICE simulation, and the proposed P/G supply voltage degradation aware placement achieves an average of 20.9% (11.7%) reduction on maximum (average) supply voltage degradation with only 4.3% wirelength increase.

A Sub-1-V, 10 ppm/<formula formulatype="inline"> <tex>$^{\circ}$</tex></formula>C, Nanopower Voltage Reference Generator

An extreme low power voltage reference generator operating with a supply voltage ranging from 0.9 to 4 V has been implemented in AMS 0.35-mum CMOS process. The maximum supply current measured at the maximum supply voltage and at 80degC is 70 nA. A temperature coefficient of 10 ppm/degC is achieved as the combined effect of 1) a perfect suppression of the temperature dependence of mobility; 2) the compensation of the channel length modulation effect on the temperature coefficient; and 3) the absence of the body effect. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -53 and -42 dB, respectively. The occupied chip area is 0.045 mm2.

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.

Ultra-low-power temperature compensated voltage reference generator

A CMOS voltage reference generator, based on the difference between the gate–source voltages of two NMOS transistors, has been implemented with AMS 0.35μm CMOS technology (Vthn=0.45 and Vthp=0.75V at 0°C). The minimum and maximum supply voltages that ensure the correct operation of the reference voltage generator, are 1.5 and 4.3V, respectively. The supply current at the maximum supply voltage and at 80°C is 2.4μA. A temperature coefficient of 25ppm/°C and a line sensitivity of 1.6mV/V are achieved. The power supply rejection ratios without any filtering capacitor at 100Hz and 10MHz are larger than −74 and −59dB, respectively. The occupied chip area is 0.08mm2.

Reduced Hot Carrier Effects in Self-Aligned Ground-Plane FDSOI MOSFET’s

This paper reports the hot-carrier induced device degradation of fully depleted (FD) n-channel SOI MOSFETs with a self-aligned ground-plane electrode in the silicon substrate underneath the buried oxide. The ground-plane configuration is shown to reduce short-channel effects, BJT effects and hot-carrier effects. Based on measurements of hot-carrier degradation rate, it is predicted that the maximum allowable supply voltage of ground-plane FDSOI MOSFET is higher than that of FDSOI device without a ground plane.

A high voltage NMOSFET fabricated by using a standard CMOS logic process as a pixel‐driving transistor for the OLED on the silicon substrate

A high voltage NMOSFET is proposed to drive top emission organic light emitting device (OLED) used in the organic electroluminescent (EL) display on the single crystal silicon substrate. The high voltage NMOSFET can be fabricated by utilizing a simple layout technique with a standard CMOS logic process. It is clearly shown that the maximum supply voltage (VDD) required for the pixel‐driving transistor could reach 45 V through analytic and experimental methods. The high voltage NMOSFET was fabricated by using a standard 1.5 μm, 5 V CMOS logic process. From the measurements, we confirmed that the high voltage NMOSFET could sustain the excellent saturation characteristic up to 50 V without breakdown phenomena.

A bond-wire inductor-MOS varactor VCO tunable from 1.8 to 2.4 GHz

This paper presents a technique that optimizes LC-tank CMOS voltage-controlled oscillators (VCOs) by minimizing the product of phase noise and power consumption. Moreover, it shows that the minimum depends on the tank's quality factor Q, the device noise coefficient /spl gamma/, and the ratio between the maximum oscillation amplitude and supply voltage /spl alpha/. Prototypes, realized in a 0.35-/spl mu/m process, show the following performances: -122.5 dBc/Hz at 600 kHz from a 1.9-GHz carrier, with 2-V supply voltage and 1-mA current consumption. The VCO can be tuned between 1.8-2.4 GHz, when the varactor control voltage is varied between 0-3.5 V. In the proposed realization, the tank is made of a metal-oxide-silicon varactor (operated between accumulation and deep depletion) and a bond-wire inductor, realized connecting two pads to a package frame lead to be compatible with the production environment.

Design of Magneto-Rheological fluid based device

The effect of power supply voltage on the performance limits in a laboratory magnetorheological fluid based device was identified by experiments. It suggests that the frequency range of motion for control is limited by the voltage attenuation due to the coil inductance and the maximum power supply voltage set for practical use of an MRF devices. In this work, the magnetic and electrical characteristics of the MRF device are investigated and a design procedure is formulated to achieve the desired performance for a given power supply.

A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25-μm CMOS

A power amplifier for wireless applications has been implemented in a standard 0.25-/spl mu/m CMOS technology. The power amplifier employs class-E topology to exploit its soft-switching property for high efficiency. The finite dc-feed inductance in the class-E load network allows the load resistance to be larger for the same output power and supply voltage than that for an RF choke. The common-gate switching scheme increases the maximum allowable supply voltage by almost twice from the value for a simple switching scheme. By employing these design techniques, the power amplifier can deliver 0.9-W output power to 50-/spl Omega/ load at 900 MHz with 41% power-added efficiency (PAE) from a 1.8-V supply without stressing the active devices.

Laser oscillation using an inductive energy storage pulsed-power generator with plasma opening switch

It is believed that an inductive energy storage pulsed-power generator with storage inductor and opening switch realizes a lightweight, compact and high-power laser system. However, the technology for opening high current is rather obscure, so that the opening switch is being developed and there are few applications for using in the generator. The purpose of the research is an extension of the application field of this generator into the laser system whose market is now growing rapidly.Plasma opening switch (POS) is chosen because as reported the highest current can flow through it in many switches and it is possible to open the circuit. At first, in the experiments, a suitable discharge load was made and the practicable supply voltage and the discharge condition were examined. As a result, when the charge voltage on the main capacitance was 15 kV, the maximum supply voltage was 26 kV and the load current was 8 kA.

Scalability of Gate/N- Overlapped Lightly Doped Drain in Deep-Submicrometer Regime

In this paper an experimental study of the scalability of a gate/N- overlapped lightly doped drain (OL-LDD) structure in the deep-submicrometer regime is presented. Devices were optimized for processes with a design rule down to 0.15 µm. The allowable power supply voltage is obtained by investigating the time-dependent dielectric breakdown reliability, the minimum operating voltage, the gate-induced-drain-leakage current, the drain-induced-barrier-lowering effect and the DC hot carrier reliability. It was found that the maximum allowable supply voltage is mainly limited by the DC hot carrier reliability even in the deep-submicrometer range. A higher current-driving ability in the OL-LDD structure is achieved in comparison to that in a single drain (SD) structure when VDmax is applied as a supply voltage. The OL-LDD structure has a smaller CGD in the inversion region as well as in the accumulated region, as compared with the SD structure, especially with smaller LG. Consequently, the performance of complementary metal-oxide-semiconductor (CMOS) devices with the OL-LDD structure is superior to that with the SD structure in the deep-submicrometer regime. It is also confirmed that the OL-LDD structure has a scaling merit even for 0.15 µm CMOS devices.

Fully differential switched opamp with enhanced common mode feedback

A switched opamp with a fast common mode feedback (CMFB) circuit is presented. The proposed fully differential two stage amplifier needs CMFB only for the second stage, and thus a fast and simple passive CMFB circuit may be used. The amplifier is capable of 1 V operation and has no limitation on the maximum supply voltage.

SIGFRED: a low-power DTMF and signaling frequency detector

A CMOS circuit is presented containing an analog switched-capacitor processor for detection of dual-tone multifrequency, (DTMF) and signaling tones on a telephone subscriber line and a digital detection algorithm for postprocessing. The major issues for the design were that it should be compatible with a CMOS fabrication process for microcontrollers to be included as an on-chip component and that its power consumption should be as low as possible. It has been designed to work with a current of less than 0.5 mA at low supply voltages (2.5-3 V). The maximum supply voltage is limited to 6 V by the process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-voltage hot-electron currents and degradation in deep-submicrometer MOSFETs

Hot-electron currents and degradation in deep submicrometer MOSFETs at 3.3 V and below are studied. Using a device with L/sub eff/=0.15 mu m and T/sub ox/=7.5 nm, substrate current is measured at a drain bias as low as 0.7 V; gate current is measured at a drain bias as low as 1.75 V. Using the charge-pumping technique, hot-electron degradation is also observed at drain biases as low as 1.8 V. These voltages are believed to be the lowest reported values for which hot-electron currents and degradation have been directly observed. These low-voltage hot-electron phenomena exhibit similar behavior to hot-electron effects present at higher biases and longer channel lengths. No critical voltage for hot-electron effects (such as the Si-SiO/sub 2/ barrier height) is apparent. Established hot-electron degradation concepts and models are shown to be applicable in the low-voltage deep submicrometer regime. Using these established models, the maximum allowable power supply voltage to insure a 10-year device lifetime is determined as a function of channel length (down to 0.15 mu m) and oxide thicknesses. >

Tokamak position control

A set of sensing coils to measure plasma position is described. The possibility of placing these coils outside a vacuum vessel (as a resistive shell) is considered by analyzing a feedback system for controlling otherwise unstable axisymmetric motion. A simple model was used to study the axisymmetric stability of a noncircular plasma surrounded by a conducting vacuum vessel and a feedback control system. Suitable choice of the various constants allowed a study of either horizontally or vertically unstable motion, either with or without an iron core and with various configurations for the vacuum vessel. Analytic expressions for the stability limits are derived, together with the specific response to a requested step displacement, giving the overshoot, steady-state error, decay times, and maximum power supply voltage. By suitably choosing an effective decay index both vertical and horizontal motion were studied. The results are applied to TEXT Upgrade (horizontal elongated, with iron core, horizontal unstable) using an effective decay index of -1. >

A modified lightly doped drain structure for VLSI MOSFET's

A new n-MOS LDD-like device structure (the J-MOS transistor) is proposed. Its design, simulation, and fabrication are studied in this paper, n-channel MOSFET's with L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</inf> below 2 µm suffer from high-field effects that must be overcome to secure reliable 5-V operation. LDD structures alleviate these effects, but their reliability is better than that of conventional MOSFET's only if the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> regions have a peak doping density above 1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">18</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . To overcome this limitation and to allow constant voltage scaling for devices into the submicrometer regime, the J-MOS structure uses a series drain JFET to drop part of the supply voltage. Both 2-D device simulations and experimental results are presented to demonstrate the operation of this device and its potential for applications requiring reliable submicrometer device operation under maximum supply voltage. The major experimental findings are that the J-MOS structure can sustain 5-V operation even for submicrometer effective channel lengths. As has been the case with all LDD-like structures, improved device reliability has been achieved at the expense of some performance. However, the advantages of keeping 5-V operation in micrometer-sized devices may outweigh this performance loss.