Maximum Lateral Electric Field Research Articles

(Invited) Hot Carrier Reliability of High Voltage HVMOSFETs in BCD (Bipolar-CMOS-DMOS) Technology

This paper discusses three important issues in hot carrier (HC) reliability of LDMOSFET ((Laterally Diffused MOSFETs) in BCD technology. One of the main reliability issues encountered during development of the LDMOSFET is optimizing the trade-offs between specific on-resistance (Rdson) and hot carrier (HC) degradation [2]. For instance, Rdson can be reduced by increasing the drift region doping concentration or shrinking the drift region length. Both of these changes result in higher lateral electric field in the drift region which lead to increased HC degradation. The second issue is how to reduce HC degradation in LDMOS due to Back-End-Of-Line (BEOL). It has been reported for CMOS devices that HC performance can be degraded by BEOL processes such as interlayer dielectric film deposition, etch, metal deposition and etch process [3, 4]. The BEOL processes in BCD technology may have a worse impact on LDMOS HC performance than on CMOS’s since it has such as higher energy implants and thicker metal deposition and etch. The third issue is the influence of self heating on the measurement of HC degradation in high gate voltages stress for HC SOA (safe-operating-area) in high voltage LDMOS [5, 6]. To address the first issue, we have compared the thin gate oxide (11.5nm) and thick gate oxide (60nm) LNDMOS hot carrier degradation results as shown in Fig.1 (b). The HC degradation has been significantly reduced in thick gate oxide LNDMOS. The main reason for the reduction may be due to drift region oxide thickness. Based on the results, we proposed a new LDMOS structure in a BCD technology that improves HC degradation without sacrificing the device breakdown voltage or Rdson [1]. The process to form the thick oxide in drift region-I in the LNDMOS is the same as to form thick gate oxide MOSFET, so only a layout change is required. The 11.5nm gate oxide thickness in the channel region remains the same for both LNDMOS structures. The maximum lateral electric field Emax in drift region-I would be reduced by over 94% if the oxide thickness increased to 60nm from 11.5nm based on our calculation. TCAD simulations clearly show that impact ionization rate for the 30V LNDMOS with the thick oxide in drift region-I has been significantly reduced, and also its peak location has been pushed away from the surface into the bulk of the silicon within drift region-I as shown in Fig.2(b). For the second issue, we demonstrated a modified SiN barrier layer which can improve device hot carrier performance in the LDMOSFET. We show experimentally that using a barrier layer of SiN or SiON which is engineered to have a relatively high refractive index (RI) and electrical conductivity can reduce the BEOL effect on hot carrier performance. Increasing the SiH4 flow rate during deposition increases the film’s RI and also its electrical conductivity [9]. The increased electrical conductivity of the SiN barrier layer allows charge from plasma processing to be dissipated into the silicon. At 4000C, a typical BEOL dielectric deposition temperature, the conductivity of the SiN barrier layer is much higher. Thus, the SiN barrier layer can reduce the PPID for the oxide in drift region resulting in reduced HC degradation. The HC Idlin degradation for the LNDMOS device with thick oxide in drift region and high RI SiN or SiON barrier layer has been significantly reduced to less than 1/3 the degradation observed in the standard LNDMOS as shown in Fig.2 (a). The reduced HC Idlin degradation is about 68% due to the thick oxide in drift region-I, and about 32% from the high RI SiN barrier layer. The HC Vth (threshold voltage) degradation exhibited very small degradation after the HC stress. Our data shows self heating, caused by HC stress in the thick gate oxide HV LNDMOS, significantly affected Idlin/Rdson electrical parameter and HC degradation characteristic. The change in delay time between the removal of the HC stress after each stress cycle and the parameter measurement resulted in a significant difference in HC Idlin/Rdson degradation [6]. For a longer delay time, lower Idlin degradation was observed, see Fig.3 (a). The difference or recovery of degradation was mainly due to the self heating effect from Idlin degradation vs junction temperature change (Fig3.(b)) and temperature monitor data. The Idlin degradation from self heating effect seems to be more than from HC effect in packaged HV LNDMOS. In the final paper, we will include some methods to eliminate the self heating effect, and to separate the self heating and local HC injection effect. Figure 1

Total-Ionizing-Dose-Induced Body Current Lowering in the 130 nm PDSOI I/O NMOSFETs

The body current lowering effect of 130 nm partially depleted silicon-on-insulator (PDSOI) input/output (I/O) n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) induced by total-ionizing dose is observed and analyzed. The decay tendency of current ratio of body current and drain current is also investigated. Theoretical analysis and TCAD simulation results indicate that the physical mechanism of body current lowering effect is the reduction of maximum lateral electric field of the pinch-off region induced by the trapped charges in the buried oxide layer (BOX). The positive charges in the BOX layer can counteract the maximum lateral electric field to some extent.

Effect of source extension junction depth and substrate doping concentration on I-MOS device characteristics

Some device design issues of the impact-ionization MOS (I-MOS) device are discussed in terms of the junction depth of the source extension region and the substrate doping concentration. It is found that the source extension region is needed to be as shallow as possible in order to minimize the avalanche breakdown voltage. Furthermore, it is observed that the dependence of the threshold voltage of the I-MOS device on the substrate doping concentration is contrary to that of the MOSFET, which is an interesting phenomenon. It is related to the junction abruptness between the channel and the i-region, which is explained by using the concept of maximum lateral electric field.

Hot-carrier degradation in deep-submicrometer nMOSFETs: lightly doped drain vs. large angle tilt implanted drain

The hot-carrier degradation of lightly doped drain (LDD) and large angle tilt implanted drain (LATID) nMOSFETs of a 0.35 μm CMOS technology is analysed and compared by means of I–V characterisation and charge pumping current measurements. LATID nMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity at maximum substrate current condition. The different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage. Further to this analysis, the hot-carrier degradation comparison between LDD and LATID devices is extended to the whole range of gate-stress regimes and the effects of short electron injection (SEI) and short hole injection (SHI) phases on hot-carrier-stressed devices are analysed. Apart from a significant improved resistance to hot-carrier effects registered for LATID devices, a similar behaviour is observed for the two types of architectures. In this way, SEI phases are found to be an efficient tool for revealing part of the damage generated in stresses at low gate voltages, whereas the performance of a first SHI phase after stress at high gate bias is found to result in a significant additional degradation of the devices. This enhanced degradation is attributed to a sudden interface states build-up occurring in both, LDD and LATID devices, near the Si/spacer interface only under the first hot-hole injection condition.

Monte Carlo Study of the Lateral Distribution of Gate Current Density Along the Channel of Submicron LDD MOSFET's

This paper presents the spatial distribution of hot electrons along the channel of a 0.35 micron MOSFET using the full band pseudopotential Monte Carlo simulator DAMOCLES. The important aspect of this investigation is the implementation of a rigorous statistical enhancement technique along the channel of the device, to probe the hot electrons generated along the channel. Simulations have been carried out for different bias points. The results clearly show that the probability of generating electrons with energies sufficient for injection into the oxide layer is significant only at the drain side of the device. It is also observed that the peak gate current occurs exactly just inside the LDD region coincident with the position of maximum lateral electric field.

Hot-carrier reliability in deep-submicrometer LATID NMOSFETs

The hot-carrier degradation of large angle tilt implanted drain (LATID) NMOSFETs of a 0.35 μm CMOS technology is analysed and compared to the degradation behaviour of standard LDD devices. LATID NMOSFETs are found to exhibit a significant improvement in terms of both, current drivability and hot-carrier immunity. By means of I–V characterisation and charge pumping measurements, the different factors which can be responsible for this improved hot-carrier resistance are investigated. It is shown that this must be attributed to a reduction of the maximum lateral electric field along the channel, but not to a minor generation of physical damage for a given electric field or to a reduced I–V susceptibility to a given amount of generated damage.

Graded-junction gate/n/sup -/ overlapped LDD MOSFET structures for high hot-carrier reliability

A newly developed gate/n/sup -/ overlapped LDD MOSFET was investigated. The MOSFET was fabricated by an oblique rotating ion implantation technique. A formula for the impurity ion profile was derived to analyze the lowering of substrate current and improvement of the degradation caused by the hot-carrier effect of the MOSFET. It was proved that the impurity ion profile near the drain edge is remarkably graded in the directions along channel and toward substrate even just after the implantation, so that the maximum lateral electric field is relaxed as compared with conventional LDD MOSFETs. Also, the maximum point of the lateral electric field at the drain edge is located apart from the main path of the channel current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Lateral distribution of hot-carrier-induced interface traps in MOSFETs

The spatial profiles of hot-carrier-induced interface traps in MOSFETs with abrupt arsenic junctions and oxide thickness of 10-38 nm are determined using charge pumping both in the conventional manner and with a modified constant-field approach. For the thinnest oxides the damage is highly localized in a very sharp peak that is located inside the drain at the point of maximum lateral electric field. In thicker oxides, the damage peak is broader and is shifted toward the edge of the drain junction. Two-dimensional device simulations using the measured profiles are in qualitative agreement with measured I-V characteristics after degradation. However, the magnitude of the predicted degradation is underestimated, suggesting that significant electron trapping occurs also.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Leakage current characteristics of offset-gate-structure polycrystalline-Silicon MOSFET's

Leakage current characteristics of offset-gate-structure polycrystalline-silicon (poly-Si) MOSFET's are studied as a function of dopant concentration N off in offset-gate regions. Leakage current markedly decreases from 1 × 10-9to 2 × 10-11A at V D = 10 V as N off is varied from 1 × 1018to 1 × 1017cm-3. A maximum ON/OFF current ratio of 108is obtained at 1 × 1017cm-3. Calculations based on a quasi-two-dimensional model indicate that the reduction of leakage current is attributable to a decrease of the maximum lateral electric field strength in the drain depletion region. An analysis of the leakage current characteristics in terms of carrier emission from grain-boundary traps implies that thermonic emission accompanied by thermally assisted tunneling could be the dominant mechanism in determining leakage current.

Optimum design of n+-n-double-diffused drain MOSFET to reduce hot-carrier emission

Channel electric field reduction using an n+-n-double-diffused drain MOS transistor to suppress hot-carrier emission is investigated. The double-diffused structure consists of a deep low-concentration P region and a shallow high-concentration As region. The channel electric field strongly depends on such process and device parameters as the length of the n-diffusion region, drain junction depth, gate oxide thickness, gate length, applied voltage, and P implant energy. The optimum condition for a double-diffused structure is determined based on those parameter dependences of the channel electric field. The results of the optimum drain impurity profile to give the minimum channel electric field are obtained when the maximum lateral electric field is located at the boundary between the P region and the As region. The hot-carrier immunity of MOSFET and test circuits are improved by two orders of magnitude and one order of magnitude, respectively, under the optimum conditions.