Maximum Differential Nonlinearity Research Articles

Spin–orbit torque flash analog-to-digital converter

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

A 99.93% energy-efficient switching scheme for SAR ADC without switching energy in the first three MSBs

This paper presents a highly energy-efficient and area-saving switching scheme for successive approximation register (SAR) analog-to-digital converters. By switching the voltages of all the bottom plates of capacitors in one side simultaneously by the same voltage level, the proposed switching scheme consumes no switching energy in the first three comparison cycles during which most of the switching energy is consumed. This switching method achieves a 99.93% reduction in switching energy and 97.6% less number of total capacitors over the conventional SAR switching scheme. In addition, the root mean square (RMS) of the maximum differential nonlinearity (DNL) and the maximum integral nonlinearity (INL) are 0.318 LSB and 0.32 LSB, respectively.

A 10-Bit 20 Channel LCD Column Driver Using Compact DAC

A 20-channel liquid crystal display (LCD) driver architecture is implemented with [Formula: see text]m CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using [Formula: see text]m CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140[Formula: see text]dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7[Formula: see text]V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is [Formula: see text]m and the settling time is [Formula: see text]s for the [Formula: see text] and 20[Formula: see text]pF driving load.

An 8.5 ps Resolution, Cyclic Vernier TDC Using a Stage-Gated Ring Oscillator and DWA-Based Dynamic Element Matching in 28 nm CMOS

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a stage-gated ring oscillator (SGRO) and data-weighted averaging (DWA) dynamic element matching (DEM). Using the phase-preserving characteristic of SGRO, DEM is realized using simple enable switches. DWA is achieved by storing the SGRO’s previous state and using it as the beginning state of the next conversion. This approach achieves cyclic selection of signal propagation paths in SGRO, and the systematic mismatch is averaged out through multiple conversions. DWA achieves the first-order mismatch correction, further improving linearity. Circuit techniques are presented to achieve accurate measurement by removing errors occurring in multiphase time-domain processing. A TDC fabricated with a 28-nm CMOS process is realized in a compact area of 0.0056 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurements show that the TDC achieves an 8.5-ps resolution and an 11-bit dynamic range (DR). Full range linearity measurement shows a maximum differential nonlinearity (DNL) of 0.3 LSB and integral nonlinearity (INL) of 2.3 LSB. The power consumption is only 0.198 mW at a 15-MS/s conversion rate, resulting in a favorable figure of merit (FoM) of 0.021 pJ/conversion step. The results show the effectiveness of the proposed TDC for improved linearity and resolution.

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

PurposeIn parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.Design/methodology/approachVarious low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.FindingsThis paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.Originality/valueSimulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

A 99.43% Energy Saving Switching Scheme with Asymmetric Binary Search Algorithm for SAR ADCs

In this paper, a low-energy switching scheme based on the asymmetric binary search algorithm for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. To reduce switching energy and area, the proposed scheme uses the single-side switching method and the least significant bit (LSB) capacitor is split into two one-half unit capacitors. Using the series capacitance scheme, the capacitance mismatch caused by process deviation is effectively improved. Compared with the conventional switching method, the switching energy of this scheme is decreased by 99.43% and the area is saved by 87.2%. MATLAB simulation results show that this scheme also has a low nonlinearity that the maximum differential nonlinearity is only 0.37 LSB and the maximum integral nonlinearity is only 0.43 LSB.

Current Measurement Transducer Based on Current-to-Voltage-to-Frequency Converting Ring Oscillator with Cascade Bias Circuit.

We propose a ring oscillator (RO) based current-to-voltage-to-frequency (I–V–F) converting current transducer with a cascade bias circuit. The I–V–F converting scheme guarantees highly stable biasing against RO, with a rail-to-rail output operation. This device was fabricated using National NanoFab Center (NNFC) 180 nm complementary metal-oxide-semiconductor (CMOS) technology, which achieves a current resolution of 1 nA in a measurement range up to 200 nA. A noise floor of 11.8 pA/√Hz, maximum differential nonlinearity (DNL) of 0.15 in 1 nA steps, and rail-to-rail output with a 1.8 V power supply is achieved. The proposed transducer can be effectively applied to bio-sensing devices requiring a compact area and low power consumption with a low current output. The fabricated structure can be applied to monolithic-three-dimensional integration with a bio-sensing device.

A 15ps resolution time-to-digital converter with on-chip PLL counting for LiDAR multi-object sensors

Light detection and ranging (LiDAR), as a kind of depth image processing technology, has a wide range of applications in precise range and range rate equipment (PRARE) and two-dimensional/three-dimensional imaging systems. This paper presents a high resolution time-to-digital converter (TDC) for LiDAR sensors. The count clock provided by the on-chip phase-locked loop (PLL) guarantees high resolution and reliable PVT (process, voltage and temperature) tolerance of the TDC. In particular, a novel structure of a pulse-injection ring oscillator shared by TDC and PLL is proposed to avoid frequency offsets and clock jitter caused by the use of multiple ring oscillators while saving power consumption. To satisfy the LiDAR for adjacent multi-object sensing, a fast digital shift register array is introduced. Other key circuits considered to reduce the non-linearity and bit error of TDC are described in detail. The prototype chip is fabricated in a standard 65 nm CMOS process with an area of 0.056 mm2. Using a 1.2 V supply, the TDC achieves an average power consumption of 3.36 mW. The performance of the TDC has been measured. The maximum differential nonlinearity (DNL) is 13.4ps and the maximum integral non-linearity (INL) is 32.1ps with the help of INL LUT calibration, respectively.

A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator

This brief presents a two stage open loop fractional-N frequency synthesizer using proposed injection locking phase modulator for low power applications. A novel low power injection locking oscillator (ILO)-based digital phase modulator (DPM) is proposed in this brief. The maximum differential nonlinearity (DNL) of proposed DPM is smaller than 0.3 degree in the whole range with 1.6 mW power consumption. An integer-N injection locking phase locked loop (ILPLL) is designed to generate the radio frequency signals for the second stage open loop frequency synthesizer. With an injection strength adjustment unit, the open loop fractional-N frequency synthesizer employing proposed DPM achieved excellent in band phase noise and instantaneous frequency switching with low power consumption. This frequency synthesizer is fabricated on 28-nm CMOS technology and its active area is 0.08 mm2. The output frequency range is from 320 MHz to 520 MHz and the power dissipation is 2.7 mW from 0.9 V supply in fractional-N mode. The measured RMS jitter integrated phase noise from 10 KHz to 40 MHz of 440 MHz and 440.4 MHz carrier frequency are 3.8 ps and 17.6 ps, respectively. The corresponding figure of merits (FoM) are −231 dB and −211 dB, respectively.

Energy-efficient and two-step structure switching scheme based on reference-free for SAR ADC

A novel capacitor switching scheme for successive approximation register analogue-to-digital converters is proposed which can achieve a high energy saving, with only two references, Vref and gnd. Due to the two-step architecture is adopted here, the total capacitance is reduced by 48.44% over the conventional structure. Furthermore, based on the most-significant bit capacitor using split-capacitor procedure and monotonic switching method, the proposed switching scheme achieves 99.74% less switching energy over the conventional architecture. Note that during the design procedure, the complexity of logic and auxiliary power supply circuits are further reduced by the lack of the common voltage (Vcm). Besides the significant energy saving in the switching process, the proposed capacitor architecture also has zero consumption in reset energy. Matlab simulation results show the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.644 LSB and 0.825 LSB.

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

A novel switching scheme with proportional coefficient for successive approximation register analog-to-digital converter is presented in this work. The proposed switching scheme realize proportional coefficient by means of charge-sharing, which can achieve a high energy efficiency. Due to the split capacitor array structure is adopted here, the total capacitance can be reduced by 96.9% over the conventional structure. Moreover, the bridge capacitor is the unit capacitor, which is very convenient for layout design and capacitance matching. Furthermore, the proposed switching scheme reduces the energy by 99.9% compared with the conventional architecture through using the MSB-split switching structure and the single-side method. The proposed switching scheme also has a good performance in reset energy consumption and linearity. Based on the MATLAB simulation results, the maximum differential nonlinearity and maximum integral nonlinearity results of the proposed switching scheme are 0.626 LSB and 0.727 LSB, respectively.

Energy-efficient switching scheme based on floating technique for SAR ADC

A high energy-efficiency capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters is proposed in the paper. During the design procedure, the charge characteristic of the floating capacitor and the technique of splitting capacitor ensure zero energy consumption of switching operation. With the reset energy of capacitor arrays taken into account, the proposed switching scheme can achieve 100% less switching energy over the conventional switching scheme. Furthermore, this work also achieves about 50% area reduction with only two reference voltages. The behavioral simulation of the proposed SAR was performed, the maximum differential nonlinearity and maximum integral nonlinearity are 0.451 and 0.452 LSB respectively.

Energy-Efficient and Area-Saving Asymmetric Capacitor Switching Scheme for SAR ADCs

An asymmetric architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) are proposed. The novel architecture achieves 81.25% reduction in capacitor area over the convention SAR. With the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 99.01% less switching energy over the convention SAR. Besides the significant energy saving, this asymmetric capacitor architecture also obtains a good performance in nonlinearity simulation. Based on the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.166LSB and 0.122LSB, respectively.

An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps.

A Low-Noise &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$RC$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Based Phase Interpolator in 16-nm CMOS

This brief describes a passive analog phase interpolator, utilizing a switched ${RC}$ -network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192-ps input time delta. The circuit draws 0.2 mW from a 0.8-V supply, and occupies 0.004 mm2.

8-Channel Neural Stimulation ASIC for Epidural Visual Cortex Stimulation

This paper presents an 8-channel neural stimulator application-specific integrated circuit (ASIC) for biphasic stimulation of the visual cortex, fabricated in a 0.35[Formula: see text][Formula: see text]m AMS HV process. Each channel is composed of a standard SPI interface, an 8-bit current digital-to-analog converter (DAC) and 120[Formula: see text]V compliant HV output stage. Thus, it is possible to deliver to the tissue arbitrary current waveforms with amplitudes up to [Formula: see text]8.192[Formula: see text]mA with 32[Formula: see text][Formula: see text]A steps. The measured maximum differential nonlinearity (DNL) of the current output does not exceed 1.1 LSB. The on-board current reference provides the output current of 16[Formula: see text][Formula: see text]A with a very low temperature variation. The maximum anodic and cathodic current mismatch after calibration is 25[Formula: see text][Formula: see text]A. The measured interpulse leakage current does not exceed 60[Formula: see text]pA. The ASIC was also tested with the electrode–tissue model, which describes the PEDOT electrodes of 560[Formula: see text][Formula: see text]m diameter in the phosphate buffer saline (PBS). The measurement results approve the possibility to stimulate with arbitrary current amplitudes with frequencies up to 1.5[Formula: see text]kHz.

High Temperature Data Converters in Silicon Carbide CMOS

This paper presents an 8-b digital to analog converter (DAC) and 8-b analog to digital converter (ADC) for high-temperature applications. The pair of data converters were designed in a 1.2- $\mu \text{m}$ silicon carbide CMOS process and have been tested from 25 °C to 400 °C. At 400 °C, the DAC has a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) error of 1.2 least significant bit (LSB) and 2.7 LSB, respectively, while the offset and the gain error are 5.9 and 2.7 LSB. The ADC has a maximum DNL and INL error of 3.6 and −3 LSB, respectively, while the offset error is −7 LSB and the gain error is 2.6 LSB. The ADC has an SNDR = 32.15 dB and effective number of bits = 5.05 b at 300 °C. The DAC is the first of its kind in silicon carbide CMOS, while the ADC is the first reported at temperatures over 300 °C.

A novel switching scheme and area-saving architecture for SAR ADC

A novel area-saving architecture and energy-efficient capacitor switching scheme for successive approximation register (SAR) analogue-to-digital converters is proposed. In the proposed architecture, the higher voltage potential side of the capacitor array removes the most-significant bit (MSB) capacitor. Furthermore the proposed technique achieves 81.25% reduction in capacitor area over the conventional SAR. Based on the third reference voltage VCM and split-MSB switching procedure, the proposed switching scheme achieves 98.53% less switching energy over the conventional architecture, while no reset power dissipation. Besides the significant energy saving, this asymmetric capacitor architecture also has a well performance in linearity simulation. Resulting from the Matlab simulation for capacitor mismatch, the maximum differential nonlinearity and maximum integral nonlinearity of the proposed scheme are 0.152LSB and 0.115LSB, respectively.

A Novel 10-Bit 2.8-mW TDC Design Using SAR With Continuous Disassembly Algorithm

This brief introduces a successive approximation time-to-digital converter based on a novel algorithm denoted as successive approximation register with continuous disassembly (SAR-CD). The main advantage of the proposed SAR-CD algorithm is that it moves the conditioning between the evaluated bits to the digital domain, after all the bits are evaluated. Simulation results show promising enhancements in power consumption compared with the state-of-the-art designs. A full 10-bit architecture is introduced using 65-nm CMOS technology as a case study with simulation power consumption of 2.8 mW at a sampling rate of 29.4 Msample/s from 1-V power supply with an effective number of bits value of 8.63 bits and a maximum differential nonlinearity of 1 least significant bit.