Maximum Breakdown Voltage Research Articles

Interplay between nanoparticles and water on dielectric properties of nanofluids

This paper deals with the interaction of nanoparticles (NPs) in transformer oil and water in the oil and its effect on the electrical properties of the nanoffuid (NF). The breakdown strength and dielectric spectrum measurements under AC for various concentrations of natural SiO 2 and water in mineral oil were studied. Mineral oil-based SiO 2 NFs exhibit significantly higher breakdown voltage than that of base oil under high water content. However, there is an optimal range of NP concentration and water content for maximum breakdown voltage. The results of dielectric spectrum indicate that the dielectric constants of NFs and base oil are greatly affected by water content. The real relative permittivity of oil samples increases exponentially with water content at decreasing frequency (f≤10 Hz). The imaginary relative permittivity of NFs is less than that of the base oil in all cases. Based the experimental results reported, a model on the interplay between NPs and water in transformer oil is presented. The model can broadly explain the influence of the coexistence of NPs and water on the dielectric properties of transformer oil.

Analytical Model for the SOI Lateral Power Device With Step Width Technique and High-${k}$ Dielectric

An analytical model is proposed in this paper for optimizing the breakdown voltage (BV) and drift region doping concentration of a silicon-on-insulator (SOI) lateral power device with step width technique and high- ${k}$ dielectric (SWHK device). By solving the 3-D Poisson equation, the analytical potential and the electric field distribution are investigated. The optimal width of the silicon region of each zone is calculated to obtain the maximum BV and optimal drift region doping concentration. The analytical results are well matched with the simulation results, confirming the validity of the present model. The proposed analytical model reveals the influence of step number and permittivity of high- ${k}$ dielectric on the performances of the SWHK device and provides guidance for the optimal design of the SWHK device.

Record combination fmax · Vbr of 25 THz·V in AlGaN/GaN HEMT with plasma treatment

A combination of high maximum oscillation frequency (fmax) and breakdown voltage (Vbr) was achieved in AlGaN/GaN high electron mobility transistors (HEMTs) with N2O plasma treatment on the access region. The breakdown voltage is improved from 37 V to 80 V due to the formation of oxide layer in the gate region. A suppressed current collapse is obtained due to plasma treatment on the gate-source and the gate-drain regions. The effect of the present passivation method is almost the same with that of the conventional SiN passivation method, meanwhile it can avoid introducing additional parasitic capacitance due to thinner thickness. The small signal measurement shows that HEMT can yield fT and fmax of 98 and 322 GHz, respectively, higher than that of 70 and 224 GHz for the non-treated HEMT. By using the plasma treatment technique, the HEMT can simultaneously exhibit high fmax and Vbr with a record fmax⋅Vbr of 25 THz⋅V.

Breakdown Voltage Enhancement in AlGaN/GaN High-Electron Mobility Transistor by Optimizing Gate Field-Plate Structure.

We optimize various gate head structures to improve breakdown voltage characteristics of AlGaN/GaN high-electron mobility transistors by a two-dimensional device simulator based on a T-shaped gate-connected field-plate. Field-plates (FPs) alleviate electric field spikes near the gate and drain-side overlapping edges, which eventually disperse electron avalanche and charge trapping effects. Hence, the more uniform electric field distribution provides improved breakdown voltage of the device. Multiple configurations, such as extension of the FP towards the source or drain, and symmetric extension, were investigated and compared. The best results were acquired when the FP was extended towards the drain, with an optimum length of 2 μm, which produced maximum breakdown voltage of 224 V and maximum transconductance of 132.5 mS/mm. Also, the optimum Si₃N₄ passivation layer thickness based on a T-shaped gate-connected FP structure was 50 nm.

Improved Interface Properties and Dielectric Breakdown in Recessed AlGaN/GaN MOS-HEMTs Using HfSiO<inline-formula> <tex-math notation="LaTeX">$_{{x}}$ </tex-math> </inline-formula> as Gate Dielectric

In this letter, we report optimized transport properties in gate recessed enhancement-mode GaN MOS-HEMTs by incorporating silicon into atomic layer deposited gate dielectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Compared with commonly used HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric, the interface trap density can be reduced by nearly an order of magnitude and the fixed oxide traps inside are reduced to almost half using the high-quality passivation of HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> . The MOS-HEMTs based on HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> exhibit a threshold voltage of 1.5 V, excellent subthreshold swing of 65 mV/dec, and a high on-off ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> . The incorporation of silicon in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> can also increase the dielectric breakdown property with maximum gate electric field of 2.85 MV/cm for a 10-year time-dependent gate dielectric breakdown lifetime, which is 36% higher than pure HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The maximum breakdown voltage of HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> MOS-HEMT is 742 V, which is 30% higher than HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> MOS-HEMT.

Impact of distribution of impurity particles on electric strength of transformer oil

To extend the service life and ensure the operability of oil-filled transformer equipment, the attention is paid to the development of methods for monitoring the state of oil-barrier insulation. When monitoring the technical condition of transformer oil, the class of liquid purity is determined depending on the rated voltage of the equipment. However, the influence of the parameters of mechanical impurities on the breakdown voltage is not taken into account, thereby lowering the requirements for the quality of oil barrier insulation. This makes it relevant to study the influence of the size distribution of impurity particles on the electric strength of the internal insulation of power transformers and determine the parameters of particles of mechanical impurities to justify the underestimation of the quality indicators of transformer oil in operation. Methods of mathematical statistics were employed using the Gnedenko-Weibull distribution based on the standard values of liquid purity classes. To determine the maximum and minimum voltages, the standard values of the average breakdown voltages and the results of operational tests of transformer oil in a standard spark gap were used. The relation between the particle size of mechanical impurities and the breakdown voltage of transformer oil has been established. The particle size distribution of impurities has been obtained for 12 and 13 classes of liquid purity for power transformers with a voltage of 110–750 kV. The particle size range that defines the maximum and minimum breakdown voltages has been determined, and the values of limit concentrations of mechanical particles have been established. The obtained parameters of impurity particles which determine the maximum and minimum breakdown voltages of the operating oils can be used to evaluate the technical condition when diagnosing the internal insulation of power transformers in order to increase their operational reliability, as well as to adjust the regulatory requirements for the quality of operational transformer oil according to the content of mechanical impurities.

Operational Improvement of AlGaN/GaN High Electron Mobility Transistor by an Inner Field-Plate Structure

In this study, a high-performance AlGaN/GaN high electron mobility transistor (HEMT) is presented to improve its electrical operation by employing an inner field-plate (IFP) structure. Prior to the IFP structure analysis, we compared the measured and simulated direct current characteristics of the fabricated two-finger conventional T-shaped gate HEMTs. Then, the AlGaN/GaN HEMT with a drain-side field plate (FP) structure was suggested to enhance the breakdown voltage characteristics. The maximum breakdown voltage recorded with a 0.8 μm stretched FP structure was 669 V. Finally, the IFP structure was interfaced with the gate head of the device to compensate the radio frequency characteristics, choosing the optimum length of the drain-side FP structure. Compared to the 0.8 μm stretched FP structure, the IFP structure showed improved frequency characteristics with minimal difference to the breakdown voltage. The frequency variation caused by changing the passivation thickness was also analyzed, and the optimum thickness was identified. Thus, IFP AlGaN/GaN HEMT is a promising candidate for high-power and high-frequency applications.

Study of high breakdown voltage GaN-based current-aperture vertical electron transistor with source-connected field-plates for power applications

A GaN-based current-aperture vertical electron transistor with source-connected field-plates (SFP-CAVET) is proposed and investigated by means of two-dimensional simulations. This device is characterized by the source-connected field-plates (SFP) at both sides, which leads to remarkable improvement of breakdown voltage (BV) without degradation of specific on-resistance (Ron). Systematic analyses are conducted to reveal the mechanism of the SFP modulation effect on the potential and the electric field distributions and thus the BV improvement. Optimization and design of SFP-CAVET are performed for the maximum BV. Simulation results exhibit a Ron of 2.25 mΩ · cm2 and a significantly enhanced BV of 3610 V in SFP-CAVET, indicating an average breakdown electric field of more than 240 V μm−1. Compared with conventional CAVET, both BV and average breakdown electric field in SFP-CAVET are increased by more than 121% while Ron remains unchanged. And the trade-off performance of BV and Ron in SFP-CAVET is also better than that in GaN-based CAVET with superjunctions (SJ CAVET). In addition, the fabrication process issues of the proposed SFP-CAVET are also presented and discussed. These results could break a new path to further improve the trade-off performance of BV and Ron in GaN-based vertical devices.

Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation

A new theory about terminal technology is proposed for superjunction lateral double-diffused metal–oxide–semiconductor field effect transistors with multiple floating buried layers (MFBL SJ-LDMOS) based on the bulk electric field (E-field) modulation in this paper for the first time. A concise and efficient analytical theory is presented to predict the vertical voltage and bulk E-field distributions of MFBL SJ-LDMOS. The analytical formulas for the breakdown voltage (BV) and the vertical peak E-field of MFBL SJ-LDMOS are derived in the closed-form equations, which starts from a single floating buried layer for the vertical E-field modulation, extending this theory to predict the vertical E-field peaks and vertical voltage distributions between the MFBLs. Quantitative analytical description has been given to explain the bulk E-field modulation for the MFBL. Moreover, the optimal spacing and the maximum BV are procedurally predicted. All analytical results are well verified by the 3-D numerical simulations, proving the applicability of the method presented in other power devices with MFBL including MFBL LDMOS, MFBL lateral insulated gate bipolar transistor, and MFBL diode.

X-ray radiation and runaway electron beams generated during discharges in atmospheric-pressure air at rise times of voltage pulse of 500 and 50 ns

AbstractThe parameters of X-ray radiation and runaway electron beams (RAEBs) generated at long-pulse discharges in atmospheric-pressure air were investigated. In the experiments, high-voltage pulses with the rise times of 500 and 50 ns were applied to an interelectrode gap. The gap geometry provided non-uniform distribution of the electric field strength. It was founded that at the voltage pulse rise time of 500 ns and the maximum breakdown voltage Um for 1 cm-length gap, a duration [full width at half maximum (FWHM)] of a RAEB current pulse shrinks to 0.1 ns. A decrease in the breakdown voltage under conditions of a diffuse discharge leads to an increase in the FWHM duration of the electron beam current pulse up to several nanoseconds. It was shown that when the rise time of the voltage pulse is of 500 ns and the diffuse discharge occurs in the gap, the FWHM duration of the X-ray radiation pulse can reach ≈100 ns. It was established that at a pulse-periodic diffuse discharge fed by high-voltage pulses with the rise time of 50 ns, an energy of X-ray quanta and their number increase with increasing breakdown voltage. Wherein the parameter Um/pd is saved.

New GaN based HEMT with Si3N4 or un-doped region in the barrier for high power applications

New AlGaN/GaN high electron mobility transistors (HEMTs) that their barrier layers under the gate are divided into two regions horizontally are presented in this work. Upper region is Si3N4 (SI-HEMT) or un-doped AlGaN (UN-HEMT) and lower region is AlGaN with heavier doping compared to barrier layer. Upper region in SI-HEMT and UN-HEMT reduces peak electric field in the channel and then improves breakdown voltage considerably. Lower region increases electron density in the two dimensional electron gas (2-DEG) and enhances drain current significantly. For instance, saturated drain current in SI-HEMT is about 100% larger than that in the conventional one. Moreover, the maximum breakdown voltage in the proposed structures is 65 V. This value is about 30% larger than that in the conventional transistor (50 V). Also, suggested structure reduces short channel effect such as DIBL. The maximum gm is obtained in UN-HEMT and conventional devices. Proposed structures improve breakdown voltage and saturated drain current and then enhance maximum output power density. Maximum output power density in the new structures is about 150% higher than that in the conventional.

(Invited) SiC Lateral Mosfet Implemented on Semi-Insulating Substrate

In most cases, lateral SiC MOSFETs implemented on a SiC epitaxial layer which grown on off-axis conducting substrate. For 4H-SiC, 4º-off toward <11-20> substrate is widely used in order to avoid polytype inclusion. However, step bunching often occurs during the epitaxial growth and high temperature activation process. The step bunching makes surface rough and causes scattering of carriers at the surface. Consequently, the channel mobility of the lateral MOSFET implemented on epitaxial layer grown on off-axis substrate is reduced. Therefore, on-axis substrate has advantages for improving static characteristics compared to the off-axis substrate. However, it is still possible to create polytype inclusion on an on-axis substrate during epitaxial growth, and elimination of epitaxial layer is preferred in many aspects. In this research, 4H-SiC lateral double implanted MOSFET (LDIMOSFET) have been designed and fabricated on an on-axis high purity semi-insulating (HPSI) substrate for the first time. To avoid the step bunching and polytype inclusion problem, we used on-axis SiC substrate without epitaxial layer. Figure 1 shows a cross-sectional view of the LDIMOSFET. As shown in the figure, proposed LDIMOSFET adopted a current path layer (CPL) instead of an epi-layer of the conventional lateral MOSFET. All regions of the LDIMOSFET were formed by ion-implantation. The CPL region plays an important role in obtaining MOSFET characteristics. At a forward bias condition, the CPL serves as a current path of the device, and at reverse bias condition, it serves to support the breakdown voltage. Without CPL region, only the semi-insulating layer exists between the p-base and n+ drain region. In this case, due to a low concentration of the semi-insulating substrate, small value of forward current will flow. Therefore, for obtaining desired forward and reverse characteristics, it is important to optimize the CPL parameters such as doping concentration (NCPL), depth (DCPL), and length (LCPL). To optimize the CPL parameters, device simulations were performed by using device simulator Silvaco-ATLAS. In order to obtain high breakdown voltage and low specific on-resistance, NCPL and DCPL should be within range of 2 × 1016 ≤ NCPL ≤ 4 × 1016/cm3 and 0.2 ≤ DCPL ≤ 0.3 μm, respectively. For device fabrication, considering the simulation results, we used NCPL = 2 × 1016 /cm3, and DCPL = 0.3 μm, respectively. Breakdown voltage and specific on-resistance are also depends on LCPL. Therefore, to find out the effect of LCPL on the breakdown voltage and specific on-resistance, LCPL was varied from 5 to 20 μm. For device fabrication, on-axis HPSI 4H-SiC wafers were used. To find out the effect of CPL region on the device characteristics, LDIMOSFET without CPL is also fabricated. The extracted channel mobility of the LDIMOSFET is 21.7 cm2/V∙s. The reported mobility of the Al-implanted MOSFETs fabricated on the on-axis epitaxial layer is 9 to 19 cm2/V∙s, and they explain that the mobility increase is due to the lower surface roughness. We used on-axis HPSI substrate to avoid the surface roughness scattering caused by the step bunching and we observed mobility comparable to those measured in the device implemented on the epitaxial grown on the on-axis wafer. Figure 2 shows measured IDS – VDS characteristics of the LDIMOSFET when LCPL = 5 μm. As shown in the figure, the highest drain current is 22mA/mm. In contrast, currents in the LDIMOSFET without CPL slightly increase when drain voltage exceeds 10 V. A specific on-resistance of the LDIMOSFET is 17.2 mΩ∙cm2 at VG = 25 V and VD = 1 V. When LCPL was increased from 5 to 20 μm, the specific on-resistance of the device also increased, from 17.2 to 89.8 mΩ∙cm2. The breakdown voltage of LDIMOSFET depends on LCPL, DCPL, and NCPL. Figure 3 shows measured breakdown voltage for different LCPL. As shown in the figure, longer LCPL shows higher breakdown voltage, and the maximum breakdown voltage of 1093 V was observed when LCPL = 20 μm. Maximum breakdown voltage of 1093 V was achieved with low specific on-resistance of 89.8 mΩ∙cm2 at LCPL = 20 μm. The figure of merit (BV2/Ron,sp) of the fabricated LDIMOSFET is 13.3 MW/cm2. The breakdown voltage and specific on-resistance of the device can be improved by adopting field plate and RESURF principle. The effect of the field plate and RESURF principle is under investigation. We will discuss about the detailed effects of the field plate, RESURF principle and device parameters on the static characteristics of the fabricated LDIMOSFET at the manuscript. Figure 1

The Effect of Threading Dislocation on Current-Voltage Characteristics of 3.3kV 4H-SiC Schottky Barrier Diode

Silicon carbide (SiC) is an attractive semiconductor for high-power, high-temperature, and high-frequency electronic devices due to its wide bandgap, high breakdown electric field, and high thermal conductivity. However, the development and commercialization of SiC-based devices are slow due to SiC defects. SiC growth technology has also been developed so much that killer defects, including micropipes, triangular defects and basal plane dislocation that degrade device performance, have been reduced. Although many researches have reported the degradation of devices performance caused by various crystal defects in SiC, the studies on the effect of threading dislocations (TDs) is still insufficient [1,2]. In this paper, we studied the effect of TDs on current-voltage (I-V) characteristics of 3.3 kV 4H-SiC Schottky barrier diodes (SBDs). The 3.3 kV SBDs were fabricated on a n-type 4H-SiC epitaxial wafer. The thickness of epitaxial layer was 28 um and its doping concentration 1 × 1015 cm-3. The boron (NA: 2.0 × 1018 cm-3) was implanted to form the junction termination extension (JTE) that helps to reduce electric field crowding at Schottky metal edge. The aluminum (ND,max: 5.0 × 1019 cm-3) was implanted to form ohmic contact for robust reverse blocking at the periphery of active region. The ion-implanted samples were annealed at 1700 °C for 60 m in Ar ambient. Nickel (Ni) was firstly depotied to form the front-side ohmic contact and cathod electrode, and annealed at 950 °C. Schottky metal, Ni, is deposited and then wet-etched to define the active regions. Post-annealing was performed at 300 °C. The crystal defects and process defects caused during diode fabrication on the active region were observed using electron beam induced current (EBIC) and X-ray topography (XRT). The I-V measurement were performed for forward and reverse I-V charateristics. To study the effet of dislocation on electrical properties of fabricated SBDs, I-V characteristies were analyzed. The Schottky barrier height (SBH) and ideality factor (IF) were extracted from forward characterisitics. The extracted average SBH and IF of SBDs were 1.5 eV and 1.05, respectively. The average leakage current was about 10-12 A at the reverse bias of -100V. The breakdown voltages increased with the length of JTE. The observed maximum breakdown voltage was 4.6 kV. The defects in acvitve region of all measured devices were analyzed using XRT technique to compare with electrical characteristics. The TDs did not affect the forward I-V charcteristecs. However the process defects degraded the forward characteristics, such that the ideality factor was increased from 1.05 to 1.4. These process defect significantly increased the leakage current to 10-7 A and reduced the breakdown below 1 kV. Therefore, the process defects during fabrication are fatal to the device performance. The leakage current of the devices observed TDs at active region increased compared with devices without defect. The breakdown voltage of fabricated 3.3 kV SBDs was not significantly affected by crystal defects. This meas that the TDs are not fatal defect for SBDs having rating breakdown voltage of 3.3 kV. Nevertherless, the increase in the leakage current of a device having the TDs may cause long-term reliability issues. Therfore, it is necessary to determine allowable type of defects and their defect density for highly reliable SiC power devices. [1] H. J. Jung, S. B. Yun, I. H. Kang, J. H. Moon, W. J. Kim, W. Bahng, Mater. Sci. Forum, 821-823 (2015) 563-566. [2] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, T. Endo, Appl. Phys. Lett., 100 (2012) 242102. Figure 1

2300V Reverse Breakdown Voltage Ga2O3 Schottky Rectifiers

We report field-plated Schottky rectifiers of various dimensions (circular geometry with diameter 50–200 μm and square diodes with areas 4 × 10−3–10−2 cm2) fabricated on thick (20μm), lightly doped (n = 2.10 × 1015 cm −3) β-Ga2O3 epitaxial layers grown by Hydride Vapor Phase Epitaxy on conducting (n = 3.6 × 1018 cm−3) substrates grown by Edge-Defined, Film-Fed growth. The maximum reverse breakdown voltage (VB) was 2300V for a 150 μm diameter device (area = 1.77 × 10−4 cm−2), corresponding to a breakdown field of 1.15 MV.cm−1. The reverse current was only 15.6 μA at this voltage. This breakdown voltage is highest reported for Ga2O3 rectifiers. The on-state resistance (RON) for these devices was 0.25 Ω.cm2, leading to a figure of merit (VB2/RON) of 21.2 MW.cm−2. The Schottky barrier height of the Ni was 1.03 eV, with an ideality factor of 1.1 and a Richardson's constant of 43.35 A.cm−2.K−2 obtained from the temperature dependence of the forward current density. The breakdown voltages for the different size devices ranged from 1400–2300V, with a general, but not linear trend of decreasing breakdown voltage for larger area rectifiers. The reverse recovery time was ∼22 ns for switching from +2 V to −2 V.

Geometrical effects in JTE rings termination for 4H-SiC medium-voltage devices

Compared with a conventional junction termination extension (JTE) structure, JTE rings termination used in power devices could achieve a higher blocking performance without any extra processing. In this paper, the geometrical effects in JTE rings are analyzed and demonstrated for medium voltage applications of 4H-SiC power devices. According to the simulation results, it is found that the first space (D1) of JTE rings has a strong effect on both the maximum breakdown voltage and the optimal implantation dose window. To achieve excellent blocking characteristics, D1 should kept at around 2 μm which could be implemented conveniently by contact lithography. Furthermore, the optimized design of JTE rings is verified by experimental results of 4H-SiC bipolar junction transistors (BJTs) with drifting layer of 20 μm-thickness and doping concentration of 3 × 1015 cm−3. The measured breakdown voltages are consistent with the observations from simulation results.

Simulation study of high‐reverse blocking AlGaN/GaN power rectifier with an integrated lateral composite buffer diode

In this study, a novel AlGaN/GaN power rectifier with an integrated lateral composite buffer diode (IBD-Rectifier) for reverse blocking capability improvement is proposed and investigated by Sentaurus simulations (this paper includes only simulated data and no real experimental result). AlGaN buffer layer under the anode is adopted to realise great high reverse blocking capability. A minimum turn-on voltage of 0.6 V and a maximum breakdown voltage (BV) >1.3 kV are simultaneously obtained in the IBD-Rectifier, resulting in a high Baliga's figure of merits BV 2/R on,sp (R on,sp is specific-on resistance) of ∼3000 MW/cm2. In comparison with MIS-gated hybrid anode diode and conventional schottky barrier diode, the IBD-Rectifier delivers an excellent theoretical method to achieve superior performances in high-efficiency GaN power applications.

Dimension Effect on Breakdown Voltage of Partial SOI LDMOS

Dimension effect on breakdown voltage (BV) of lateral double-diffused metal-oxide–semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is comprehensively studied. The maximum BV (BVmax) is examined under various settings of the device length ${L}$ and the active silicon film thickness ${t}$ . It is shown that there exists an optimal pair of ( ${L}$ , ${t}$ ) for PSOI at which the highest BV can be achieved. The ratio of ${L}$ / ${t}$ is better chosen between 5 and 7 for the device designs, in particular, $L/t={\mathrm{ 6}}$ can be considered as the optimal one theoretically. Moreover, impacts of the silicon window length $L_{w}$ and the drift doping concentration $N_{dr}$ on the BV, the on-resistance ( $R_{\mathrm{ on}}$ ) and the figure-of-merit ( $=\!{\mathrm{ BV}}^{2}/R_{\mathrm{ on}}$ ) are also carefully studied.

High breakdown voltage lateral AlGaN/GaN high electron mobility transistor with p-GaN islands buried buffer layer for power applications

The relatively low breakdown voltage (BV) seriously restricts the high power application of GaN based high electron mobility transistors (HEMTs). In this work, a novel AlGaN/GaN HEMT with buried p-n junctions is investigated to improve the breakdown characteristics by introducing six equidistant p-GaN islands buried buffer layer (PIBL) into the n-GaN epitaxial layer. The p-GaN islands act as reversed p-n junctions, which produces new electric field peaks at the edges of p-GaN islands, then realizing a much high breakdown voltage, and the reversed p-n junctions can help to suppress punch-through effect in buffer layer. Furthermore, the characteristics of proposed device are analyzed in detail from the aspects of off-state I-V characteristics, equipotential contour distribution, off-state electric field distribution, offstate carrier distribution and output characteristics. Simulated equipotential contour distribution shows that under the condition of high-voltage blocking state, multiple reverse p-n junctions introduced by the buried p-GaN islands produce five new electric field peaks, realizing a more uniform equipotential contour distribution especially at the edges of the buried p-islands. Then off-state electric field distribution demonstrates that p-GaN islands modulate the surface and bulk electric fields, which makes the voltage distributed in a larger area, therefore presenting a much higher breakdown voltage. It can be seen from off-state carrier distribution that the electrons in the buffer layer fully depleted in PIBL HEMT effectively suppress the buffer leakage current, thus alleviating the buffer-leakage-induced impact ionization leading to a high breakdown BV of over 1700 V with gate-to-drain length of 10μm, which is nearly 3 times larger than BV of 580 V in conventional AlGaN/GaN HEMT. Although, the introduction of p-type buried layer narrows the current path and causes an improved on-resistance, simulation shows that the specific on-resistance (Ron,sp) of PIBL HEMT is only about 1.47 mΩ·cm2, while the BV of the PIBL device is over 1700 V, and the obtained figure of merit (FOM=BV2/Ron,sp) reaches as high as 1966 MW·cm-2. The optimization of device structure reveals that when the distance between p-GaN layer and AlGaN layer (t) is 0.2μm, a thinner buried p-GaN island (tp) should help to realize a more significant electric field modulation, and PIBL HEMT can achieve a maximum BV of 1789 V with a tp=0.1μm. Compared with the traditional AlGaN/GaN HEMT, the PIBL HEMT reveals a higher breakdown voltage, meanwhile ensuring low Ron,sp, which makes this structure a promising candidate in the applications of high power electronic devices.

Experimental study on the 4H-SiC-based VDMOSFETs with lightly doped P-well field-limiting rings termination

A lightly doped P-well field-limiting rings (FLRs) termination on 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) has been investigated. Based on the simulation, the proposed termination applied to 4H-SiC VDMOSFET could achieve an almost same breakdown voltage (BV) and have the advantage of lower ion-implantation damage comparing with P+ FLRs termination. Meanwhile, this kind of termination also reduces the difficulty and consumption of fabrication process. 4H-SiC VDMOSFETs with lightly doped P-well (FLRs) termination have been fabricated on 10μm thick epi-layer with nitrogen doping concentration of 6.2×1015cm−3. The maximum breakdown voltage of the 4H-SiC VDMOSFETs has achieved as high as 1610V at a current of 15μA, which is very close to the simulated result of 1643V and about 90% of the plane parallel breakdown voltage of 1780V. It is considered that P-well FLRs termination is an effective, robust and process-tolerant termination structure suitable for 4H-SiC VDMOSFET.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.