Maximum A Posteriori Probability Decoder Research Articles

Performance Analysis of High Throughput MAP Decoder for Turbo Codes and Self Concatenated Convolutional Codes

The effect of parallelism on Bit Error Rate (BER) performance of Turbo Code (TC) and Self Concatenated Convolutional Code (SECCC) with different levels of parallelism and frame sizes is investigated. Next Iteration Initialization (NII) method is employed for mitigating the BER degradation resulting from increased parallelism. In order to analyze and compare the architectural performance of both schemes, this paper presents the Very High Speed Integrated Circuit Hardware Description Language (VHDL) design of Maximum Aposteriori Probability (MAP) decoder for TC and SECCC, both employing the same constituent code. The simulation results show that for BER of 10−4, without parallelism, TC is 0.4 dB superior to SECCC, whereas, with parallelism of 64, the difference in performance between both schemes reduces to 0.25 dB. It is found that SECCC outperforms TC for frame sizes less than or equal to 2048 bits, when invoking a parallelism of 16, 32 and 64. The BER performance of both schemes shows that SECCC outperforms TC at parallelism of 256 by 0.3 dB at BER of 10−4. Hence, for high throughput architectures employing higher parallelism (beyond 64 and 128) without significant degradation in BER performance, SECCC performs better than TC. The synthesis results of VHDL design of the MAP decoder obtained using Xilinx ISE verify that both schemes have equal clock frequency and resource consumption. It is demonstrated that the MAP decoder achieves the clock frequency of 86.3 MHz which is capable of producing a throughput of 691 Mbps using parallelism of 64.

Duality of channel encoding and decoding ‐ Part I: rate‐1 binary convolutional codes

AbstractIn this paper, we revisit the forward, backward and bidirectional Bahl–Cocke–Jelinek–Raviv (BCJR) soft‐input soft‐output (SISO) maximum a posteriori probability (MAP) decoding process of rate‐1 binary convolutional codes. From this, we establish some interesting explicit relationships between encoding and decoding of rate‐1 convolutional codes. We observe that the forward and backward BCJR SISO MAP decoders can be simply represented by their dual SISO channel encoders using shift registers in the complex number field. Similarly, the bidirectional MAP decoding can be implemented by linearly combining the shift register contents of the dual SISO encoders of the respective forward and backward decoders. The dual encoder structures for various recursive and non‐recursive rate‐1 convolutional codes are derived. Copyright © 2016 John Wiley & Sons, Ltd.

Duality of channel encoding and decoding—Part II: rate‐1 non‐binary convolutional codes

AbstractThis is the second part of a series of papers on a revisit to the bidirectional Bahl–Cocke–Jelinek–Raviv (BCJR) soft‐in‐soft‐out maximum a posteriori probability (MAP) decoding algorithm. Part I revisited the BCJR MAP decoding algorithm for rate‐1 binary convolutional codes and proposed a linear complexity decoder using shift registers in the complex number field. Part II proposes a low complexity decoder for rate‐1 non‐binary convolutional codes that achieves the same error performance as the bidirectional BCJR soft‐in‐soft‐out MAP decoding algorithm. We observe an explicit relationship between the encoding and decoding of rate‐1 convolutional codes in GF(q). Based on this relationship, the BCJR forward and backward decoding are implemented by dual encoders using shift registers whose contents are vectors of complex numbers. The input to the dual encoders is the probability mass function of the received symbols, and the output of the dual encoders is the probability mass function of the information symbols. The bidirectional BCJR MAP decoding is implemented by linearly combining the shift register contents of the dual encoders for forward and backward decoding. The proposed decoder significantly reduces the computational complexity of the bidirectional BCJR MAP algorithm from exponential to linear with constraint length of convolutional codes. To further reduce complexity, fast Fourier transform is applied. Mathematical proofs and simulation results are provided to validate our proposed decoder. Copyright © 2016 John Wiley & Sons, Ltd.

Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders

Wireless communication standards make use of parallel turbo decoder for higher data rate at the cost of large hardware resources. This paper presents a memory-reduced back-trace technique, which is based on a new method of estimating backward-recursion factors, for the maximum a posteriori probability (MAP) decoding. Mathematical reformulations of branch-metric equations are performed to reduce the memory requirement of branch metrics for each trellis stage. Subsequently, an architecture of MAP decoder and its scheduling based on the proposed back trace as well as branch-metric reformulation are presented in this work. Comparative analysis of bit-error-rate (BER) performances in additive white Gaussian noise channel environment for MAP as well as parallel turbo decoders are carried out. It has shown that a MAP decoder with a code rate of 1/2 and a parallel turbo decoder with a code rate of 1/3 have achieved coding gains of 1.28 dB at a BER of 10$$^{-5}$$-5 and of 0.4 dB at a BER of 10$$^{-4}$$-4, respectively. In order to meet high-data-rate benchmarks of recently deployed wireless communication standards, very large scale integration implementations of parallel turbo decoder with 8---64 MAP decoders have been reported. Thereby, savings of hardware resources by such parallel turbo decoders based on the suggested memory-reduced techniques are accounted in terms of complementary metal oxide semiconductor transistor count. It has shown that the parallel turbo decoder with 32 and 64 MAP decoders has shown hardware savings of 34 and 44 % respectively.

MAP detection for impairment compensation in coherent WDM systems

We propose a novel recursive-algorithm based maximum a posteriori probability (MAP) detector in spectrally-efficient coherent wavelength division multiplexing (CoWDM) systems, and investigate its performance in a 1-bit/s/Hz on-off keyed (OOK) system limited by optical-signal-to-noise ratio. The proposed method decodes each sub-channel using the signal levels not only of the particular sub-channel but also of its adjacent sub-channels, and therefore can effectively compensate deterministic inter-sub-channel crosstalk as well as inter-symbol interference arising from narrow-band filtering and chromatic dispersion (CD). Numerical simulation of a five-channel OOK-based CoWDM system with 10Gbit/s per channel using either direct or coherent detection shows that the MAP decoder can eliminate the need for phase control of each optical carrier (which is necessarily required in a conventional CoWDM system), and greatly relaxes the spectral design of the demultiplexing filter at the receiver. It also significantly improves back-to-back sensitivity and CD tolerance of the system.

Fast performance estimation of block codes

Importance sampling is used in this paper to address the classical yet important problem of performance estimation of block codes. Simulation distributions that comprise discrete- and continuous-mixture probability densities are motivated and used for this application. These mixtures are employed in concert with the so-called g-method, which is a conditional importance sampling technique that more effectively exploits knowledge of underlying input distributions. For performance estimation, the emphasis is on bit by bit maximum a-posteriori probability decoding, but message passing algorithms for certain codes have also been investigated. Considered here are single parity check codes, multidimensional product codes, and briefly, low-density parity-check codes. Several error rate results are presented for these various codes, together with performances of the simulation techniques.

MAP Decoding of Variable Length Codes With Self-Synchronization Strings

Maximum a posteriori probability (MAP) decoding of Huffman-equivalent variable-length codes (VLCs) has two undesired features. One is the high decoding complexity, and the other is the discrepancy between the objective of MAP decoding and the Levenshtein distance which is commonly used as the performance metric. In this correspondence, improvement over these two issues is targeted through extracting self-synchronization information in VLC coded sequence and incorporating it into MAP decoding. It shown that self-synchronization strings (SSSs) are concatenation of Huffman codewords and can be readily found. Occurrence probabilities of SSSs are then analyzed. By using this self-synchronization information, MAP decoding is split into multiple decoding of short data segments so that both decoding performance improvement and complexity reduction are obtained. Simulation results demonstrate the effectiveness of the proposed method.

Joint source and channel decoding with symbol re-alignment

The maximum a-posteriori probability (MAP) decoding of Huffman variable-length codes (VLCs) has been widely used in the joint source and channel decoding. This method exploits both source memory information and channel status information, but does not consider the symbol re-alignment as the conventional Huffman decoding does. In this letter, we show that self-synchronization strings (SSSs) of VLCs can be readily found and used with the MAP decoding. As a result, the performance of symbol error rate based on Levenshtein distance can be improved, with reduced decoding complexity.

Area-efficient high-throughput MAP decoder architectures

Iterative decoders such as turbo decoders have become integral components of modern broadband communication systems because of their ability to provide substantial coding gains. A key computational kernel in iterative decoders is the maximum a posteriori probability (MAP) decoder. The MAP decoder is recursive and complex, which makes high-speed implementations extremely difficult to realize. In this paper, we present block-interleaved pipelining (BIP) as a new high-throughput technique for MAP decoders. An area-efficient symbol-based BIP MAP decoder architecture is proposed by combining BIP with the well-known look-ahead computation. These architectures are compared with conventional parallel architectures in terms of speed-up, memory and logic complexity, and area. Compared to the parallel architecture, the BIP architecture provides the same speed-up with a reduction in logic complexity by a factor of M, where M is the level of parallelism. The symbol-based architecture provides a speed-up in the range from 1 to 2 with a logic complexity that grows exponentially with M and a state metric storage requirement that is reduced by a factor of M as compared to a parallel architecture. The symbol-based BIP architecture provides speed-up in the range M to 2M with an exponentially higher logic complexity and a reduced memory complexity compared to a parallel architecture. These high-throughput architectures are synthesized in a 2.5-V 0.25-/spl mu/m CMOS standard cell library and post-layout simulations are conducted. For turbo decoder applications, we find that the BIP architecture provides a throughput gain of 1.96 at the cost of 63% area overhead. For turbo equalizer applications, the symbol-based BIP architecture enables us to achieve a throughput gain of 1.79 with an area savings of 25%.

A 285-MHz pipelined MAP decoder in 0.18-/spl mu/m CMOS

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP) decoder IC. The 8.7-mm/sup 2/ IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS technology and consumes 330 mW at maximum frequency. The MAP decoder chip features a block-interleaved pipelined architecture, which enables the pipelining of the add-compare-select kernels. Measured results indicate that a turbo decoder based on the presented MAP decoder core can achieve: 1) a decoding throughput of 27.6 Mb/s with an energy-efficiency of 2.36 nJ/b/iter; 2) the highest clock frequency compared to existing 0.18-/spl mu/m designs with the smallest area; and 3) comparable throughput with an area reduction of 3-4.3/spl times/ with reference to a look-ahead based high-speed design (Radix-4 design), and a parallel architecture.

Tight Bounds for LDPC and LDGM Codes Under MAP Decoding

A new method for analyzing low density parity check (LDPC) codes and low density generator matrix (LDGM) codes under bit maximum a posteriori probability (MAP) decoding is introduced. The method is based on a rigorous approach to spin glasses developed by Francesco Guerra. It allows to construct lower bounds on the entropy of the transmitted message conditional to the received one. Based on heuristic statistical mechanics calculations, we conjecture such bounds to be tight. The result holds for standard irregular ensembles when used over binary input output symmetric channels. The method is first developed for Tanner graph ensembles with Poisson left degree distribution. It is then generalized to `multi-Poisson' graphs, and, by a completion procedure, to arbitrary degree distribution.

Joint source-channel decoding for mpeg-4 video transmission over wireless channels

This paper investigates the use of joint source-channel coding for reliable transmission of MPEG-4 video over wireless channels. We present a maximum a posteriori probability (MAP) based, joint source-channel decoder (JSCD) for variable length coded intra macroblocks and inter macroblocks in a MPEG-4 encoded video stream. We then provide a comprehensive evaluation of this paradigm as an alternative method for achieving error resilience. In particular, our method is tested in conjunction with the MPEG-4 error resilience tools such as reversible variable length codes (RVLC), resynchronization markers, and data partitioning, with and without forward error controls (FECs) and, finally, without the use of RVLCs (only variable length codes). In addition, the JSCD algorithm is tested with and without the use of FECs [Reed-Solomon (RS) codes]. These tests show that the best performance at high channel bit-error rate is obtained when all error resilience tools are co-opted. The maximum improvement due to the proposed decoder when used without FEC is about 7 dB for RVLC and 8 dB for VLCs. These numbers are about 2.2 and 7.5 dB, respectively, when the MAP decoder is used in conjunction with the RS codes.

Adaptive SNR algorithm for turbo codes

The sensitivity of the iterative maximum a posteriori probability (MAP) decoder to the initial channel values is investigated and a simple adaptive signal-to-noise ratio (SNR) algorithm operating within the delta variances from two MAP decoders is proposed. It can improve the BER by about 0.3 dB without much additional hardware complexity.

Dynamic Programming in Digital Communications: Viterbi Decoding to Turbo Multiuser Detection

Many important signal processing tasks in digital communications are based on integer programming problems whose raw complexity is extremely high. Such problems include the decoding of convolutional codes, channel equalization, multiuser detection, and the joint performance of these tasks. In each of these problems, the high complexity arises from the need to perform simultaneous processing on long sequences of finite-valued symbols in order to optimally detect or decode them. Fortunately, the complexity of these optimization problems can often be greatly reduced through the use of dynamic programming, which efficiently finds optimal [e.g., maximum likelihood (ML) or maximum a posteriori probability (MAP)] decisions in long sequences of symbols. This paper reviews four decades of progress in this area: the Viterbi algorithm for ML decoding of convolutional codes of the 1960s; the ML sequence detectors for channel equalization and the BCJR algorithm for MAP decoding of convolutional codes of the 1970s; the ML and MAP multiuser detectors of the 1980s; and combinations of these through the turbo processing of the 1990s.

Minimum mean squared error equalization using a priori information

A number of important advances have been made in the area of joint equalization and decoding of data transmitted over intersymbol interference (ISI) channels. Turbo equalization is an iterative approach to this problem, in which a maximum a posteriori probability (MAP) equalizer and a MAP decoder exchange soft information in the form of prior probabilities over the transmitted symbols. A number of reduced-complexity methods for turbo equalization have been introduced in which MAP equalization is replaced with suboptimal, low-complexity approaches. We explore a number of low-complexity soft-input/soft-output (SISO) equalization algorithms based on the minimum mean square error (MMSE) criterion. This includes the extension of existing approaches to general signal constellations and the derivation of a novel approach requiring less complexity than the MMSE-optimal solution. All approaches are qualitatively analyzed by observing the mean-square error averaged over a sequence of equalized data. We show that for the turbo equalization application, the MMSE-based SISO equalizers perform well compared with a MAP equalizer while providing a tremendous complexity reduction.

Joint decoding and carrier phase recovery algorithm for turbo codes

In this letter, we investigate the sensitivity of the iterative maximum a posteriori probability (MAP) decoder to carrier phase offsets and propose simple carrier phase recovery algorithms operating within the iterative MAP decoding iterations. The algorithms exploit the information contained in the extrinsic values generated within the iterative MAP decoder to perform carrier recovery, thus requiring low hardware complexity.

MAP algorithms for decoding linear block codes based on sectionalized trellis diagrams

The maximum a posterioriprobability (MAP) algorithm is a trellis-based MAP decoding algorithm. It is the heart of turbo (or iterative) decoding that achieves an error performance near the Shannon limit. Unfortunately, the implementation of this algorithm requires large computation and storage. Furthermore, its forward and backward recursions result in a long decoding delay. For practical applications, this decoding algorithm must be simplifled and its decoding complexity and delay must be reduced. In this paper, the MAP algorithm and its variation's, such as log-MAP and max-log-MAP algorithms, are first applied to sectionalized trellises for linear block codes and carried out as two-stage decodings. Using the structural properties of properly sectionalized trellises, the decoding complexity and delay of the MAP algorithms can be reduced. Computation-wise optimum sectionalizations of a trellis for MAP algorithms are investigated. Also presented in this paper are bidirectional and parallel MAP decodings.

Iterative MAP decoding for serial concatenated convolutional codes

The paper provides detailed computational steps for implementing an iterative serial concatenated convolutional code (SCCC) decoder. These are based on maximum a posteriori probability (MAP) decoding of a single, rate 1/2, recursive, systematic convolutional code, which is reduced to easily implemented equations for forward and backward recursion. In particular, the crucial information exchange between MAP decoders is clarified. Simulation of a rate 1/3 SCCC with memory-2 codes and a coding delay of N = 1000 shows a bit error rate of 10-6 for Eb/N0 = 1.5 dB, and gives a typical interleaver gain of N-3.