Capacitance Matching Research Articles

Leakage Current and Floating Gate Capacitor Matching Test

Capacitor mismatch is an important device parameter for precision analog applications. In the last ten years, the floating gate measurement technique has been widely used for its characterization. In this paper we describe the impact of leakage current on the technique. The leakage can come from, for example, thin gate oxide MOSFETs or high dielectric constant capacitors in advanced technologies. SPICE simulation, bench measurement, analytical model and numerical analyses are presented to illustrate the problem and key contributing factors. Criteria for accurate capacitor systematic and random mismatch characterization are developed, and practical methods of increasing measurement accuracy are discussed.

An approximation algorithm to improve capacitance matching in the design of SC filters

A critical issue in the design of switched-capacitor (SC) filters is the capacitance matching, because the filter coefficients depend on capacitance ratios. The most successful design method to achieve an accurate capacitance matching employs a parallel arrangement of identical unit capacitors to implement each filter capacitor. However, this procedure can be directly applied only if the filter coefficients can be written as rational numbers, since each capacitor is implemented as an integer number of unit capacitors in parallel. This paper presents a systematic procedure, with low computational effort, to approximate the filter coefficients by integer ratios causing acceptable errors in the filter frequency response, whereas keeping the total number of unit capacitors small, in order to save die area. This procedure was applied in the design of a sixth-order SC band-pass filter, which has been fabricated in a 0.35 μm CMOS technology. The fabricated filter occupies an area of 0.913 mm2, exhibits low sensitivity to fabrication process deviations and has an output dynamic range of 79.2 dB.

MATCHING NETWORKS IMPLEMENTED WITH HIGH-K CAPACITORS FOR HIGH FREQUENCY AMPLIFIERS

ABSTRACT Ferroelectric capacitors in the paraelectric phase can be used to implement a wide variety of tunable radio frequency (RF) circuits. Due to their low loss, fast tuning speed, size and low cost, thin film high-K capacitor is promising technology for the development of tunable filters, active and passive filters and voltage controlled oscillators. This paper presents an electronically tunable matching network for broadband amplifier for RF applications, utilizing thin-film Barium Strontium Titanate (BST) tunable capacitors. The performance of tunable matching network implemented tunable BST capacitor was compared with that of conventional p-n junction varactor.

Optimal Capacitive Load Matching of Micro Electret Power Generators

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Analysis of the Tore Supra ICRF antenna with TOPICA

The Tore Supra (CEA) antenna for the ion cyclotron range of frequencies (ICRF) is a so-called resonant double loop antenna with internal matching capacitors. The required capacitance range is crucial for antenna and the tuning-and-matching network design. The capacitance value for a given discharge is also important for antenna operation. We discuss a method to accurately predict the tuning capacitance values in the presence of plasma operation and for efficiently accounting for the capacitors in the performance analysis. The presented method relies on the use of the TOPICA code, a numerical suite developed for prediction and analysis of modern ICRF antenna systems; it is able to handle antennas with a realistic 3D geometry and an accurate 1D plasma model. Very good agreement with the experimental capacitance values is found using TOPICA, providing further experimental validation of the computational algorithm and physics model.

A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching

Using statistical matching properties of capacitor arrays, a pipelined ADC self-configures the multiplying digital-to-analog converter (MDAC) capacitor array for best matching from many trial combinations of smaller capacitive sub-elements. These sub-elements having opposite error magnitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements. The proposed state machine based permutation algorithm allows near unique permutations of the sub-elements and achieves a near unity state repetition ratio with a simple hardware implementation. An analog-to-digital converter (ADC) system is designed with the self-configuration algorithm contained in the same die, and improvement in capacitor matching is demonstrated after the self-configuration process. A 0.18-mum CMOS prototype achieves 13-b linearity and over 80-dB spurious-free dynamic range (SFDR) at 43 MS/s. The chip consumes 268 mW at 1.8 V and occupies 3.6 mm2.

Selecting an appropriate ESD protection for discrete RF power LDMOSTs

For ESD protections of RF Power MOSTs, V t1 lowering by the RF signal – due to the d V/d t effect – can seriously degrade the RF performance. The use of a cascoded protection solves this problem. A new failure mechanism, related to the discharge of on-chip RF matching capacitors is presented. Adding a current limiting resistor in the protection solves this issue. Combining these solutions yields an appropriate protection for discrete RF power LDMOSTs.

Metallorganic Chemical Vapor Deposition of Sr-Ta-O and Bi-Ta-O Films for Backend Integration of High-k Capacitors

Dielectric layers with high dielectric constant, low leakage, and high breakdown strength are of great interest for application in devices such as Dynamic random access memory, decoupling capacitors, or impedance matching capacitors. However, some applications require complementary metal oxide semiconductor backend integration of those capacitors, with low-temperature processing. In this work, we prepare and capacitors on silicon, where dielectrics are deposited at by metallorganic chemical vapor deposition (MOCVD). After capacitor fabrication, a minimal leakage is obtained for a recovery anneal at a temperature of for and for . We show that both types of dielectrics are promising for incorporation in backend integrated high- capacitors. Particularly, their leakage level is lower than reported for other dielectrics, which constitutes a significant advantage for memory application. The results also suggest that MOCVD is a suited technique to obtain very thin and films which are dense, smooth, and with good interfacial quality.

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.

Improvement in retention time of metal–ferroelectric–metal– insulator–semiconductor structures using MgO doped Ba0.7Sr0.3TiO3 insulator layer

We report the results of the fabrication and characterization of Pt/Bi3.35La0.85Ti3O12 (BLT)/LaNiO3 (LNO)/Ba0.7Sr0.3TiO3 (BST)/Si metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structures for ferroelectric memory field effect transistor applications. The BLT films were deposited on LNO/BST/Si using the metalorganic decomposition method and annealed by rapid thermal annealing (RTA) process at 600 °C for 3 min. The ratio of remanent polarization to saturation polarization (Pr/Ps) increases with reducing area ratio, AF/AI. A large memory window of 3.1 V can be obtained for a small AF/AI ratio. By the utilization of 5 mol % MgO doped BST insulator layer, LNO bottom electrode layer for BLT, and small area ratio, AF/AI=1/12 in the MFMIS structure, large Pr/Ps ratio in BLT film and low leakage current and good capacitance matching of the ferroelectric and the insulator in the MFMIS structures have been achieved and, hence, long data retention time >106 s has been obtained in this study. Experimental results demonstrate the significant progress in increase of the retention time of these structures, which make them attractive for practical ferroelectric memory field effect transistor applications.

Charge-sensitive preamplifier with continuous reset by means of the gate-to-drain current of the JFET integrated on the detector

In this paper, we present a charge-sensitive preamplifier designed for a silicon drift detector (SDD), where both input n-JFET and feedback capacitor are integrated directly on the detector chip. The integration of these devices allows obtaining a capacitive matching between detector and front-end transistor and to minimize the stray capacitances of the connections. A continuous discharging mechanism for the leakage current and for the signal charge is obtained by means of the gate-to-drain current of the front-end JFET. This current is originated by a "weak" avalanche breakdown mechanism, which occurs in a high-field region of the transistor channel. The advantage arising from the use of this mechanism is that the discharge is obtained directly by means of the front-end transistor without the need of any additional integrated device. A feedback loop in the charge preamplifier sets the suitable value of drain-gate voltage necessary to compensate for variations of the leakage current to be discharged. The first results of the experimental characterization of the SDD+preamplifier system are presented here.

Instabilities in low-pressure electronegative inductivedischarges

Plasma instabilities have been studied in low-pressure inductiveprocessing discharges with SF6 and Ar/SF6 mixtures, i.e. attachinggases. Oscillations are seen in charged particle density, electrontemperature and plasma potential using electrostatic probe and opticalemission measurements. For SF6, instability onset in pressure anddriving power has been explored for gas pressures between 2.5 and 100 mTorrand absorbed powers between 150 and 900 W. For pressures above 20 mTorr,increasing power is required to obtain the instability with increasingpressure, with the frequency of the instability increasing with pressure,mainly lying between 1 and 100 kHz. For Ar/SF6 mixtures, we observe asimilar low power transition, with an upper transition to a stableinductive mode. The instability windows become smaller as the argon partialpressure increases. For Ar/SF6 mixtures, we observe a significant effectof the matching network. We improve a previously developed volume-averaged(global) model to describe the instability. We consider a cylindricaldischarge containing time varying electrons, positive ions, negative ions,and time invariant excited states. The driving power is applied to thedischarge through a conventional L-type capacitive matching network, and weuse realistic models for the inductive and capacitive energy deposition.The particle and energy balance equations are integrated, consideringquasi-neutrality in the plasma volume and charge balance at the walls, toproduce the dynamical behaviour. As pressure or power is varied to cross athreshold, the instability is born at a Hopf bifurcation, with relaxationoscillations between higher and lower density states. The modelqualitatively agrees with experimental observations, and also shows asignificant influence of the matching network.

A 14-b 20-Msamples/s CMOS pipelined ADC

The performance of high-resolution pipelined ADCs is limited by the residue amplifier gain and settling accuracy. In typical implementations, error sources are capacitor ratio mismatch, op-amp gain, and residue settling. All these affect ADC performance adversely, specifically in high-speed ADCs. Capacitor matching improves as capacitor size increases, but the trend is towards shrinking capacitor size for high-speed conversion. Many innovations to overcome this such as ratio-independent techniques are reported. Among them, capacitor error-averaging offers an advantage of achieving both INL and DNL improvements over that achievable by capacitor matching, but it requires three clock phases-one extra clock phase for averaging capacitor errors. In this work, the one extra clock phase is used advantageously for comparison.

Fundamental frequency response bounds of direct-form recursive switched-capacitor filters with capacitance mismatch

A theoretical statistical analysis is developed to investigate the effects of random capacitance matching errors in the frequency response of recursive switched-capacitor filters implemented in direct form. As a result, with appropriate approximations, closed-form solutions for the mean and the standard deviation of the frequency response error are derived. The obtained expressions provide insight into the quantitative influence of capacitance ratio tolerance, numerator and denominator orders, passband and stopband ripples, and edge frequencies, and reveal existing tradeoffs among these parameters, so that the most efficient filter design can be found. The main theoretical results are extensively verified by simulation through Monte Carlo analysis to show the effectiveness of the proposed formulas.

A silicon drift detector with a P-type JFET integrated in the N-well anode

The work deals with calculations for and experimental results measured on a silicon drift detector having a p-type JFET integrated in its anode. A new device design and processing steps are presented based on the self-alignment of the transistor gate to the source and drain regions. The gate is formed by drive-in of phosphorus atoms from the deposited, implanted and patterned polysilicon overlayer. The accurate matching of the anode geometrical capacitance, as calculated from computer models, to the transistor capacitance is another feature of the our detector. Such improvements made possible a measured total anode capacitance of 140 fF and at the same time a transistor transconductance of 0.22 mS at room temperature.

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and successfully operated at a low voltage of 1.5 V.

A high-speed fully differential current switch

A high-speed differential-mode current switch is presented. The clock-feedthrough effect is reduced by swing-reduced drivers (SRD's) and neutralized by dummy transistors. With the use of SRD's, the switching transistors never operate in the triode region, which provides good matching of capacitance between the switching transistors and dummy transistors. The SRD's also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 59 dB dynamic range with a 50 MHz clock.

Inherently linear capacitor error-averaging techniques for pipelined A/D conversion

New passive capacitor mismatch error-averaging techniques for pipelined analog-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital converter from reaching a 10-bit and above integral nonlinearity (INL) without trimming and/or calibration. Simulation results confirm the observation and a case of 14 bit INL realized by 7 bit capacitor matching is shown. The relaxed matching requirement enables the scale-down of the capacitor sizes to that of the KT/C limit. As a result, great reductions in both power consumption and chip area can be achieved.

Electronically Tunable Surface-Coil-Type Resonator for L-Band EPR Spectroscopy

The automatic frequency control (AFC) circuit in conventional electron paramagnetic resonance (EPR) spectrometers automatically tunes the microwave source to the resonance frequency of the resonator. The circuit works satisfactorily for samples stable enough that the geometric relations in the resonance structure do not change in a significant way. When EPR signals are measured during in vivo experiments with small rodents, however, the distance between the signal source and the surface-coil detector can change rapidly. When a conventional AFC circuit keeps the oscillator tuned to the resonator under those conditions, the resultant frequency change may exceed ±5 MHz and markedly shift the position of the EPR signal. Such a shift results in unacceptable effects on the spectra, especially when the experimenter is dealing with narrow EPR lines. The animal movement also causes a mismatching of the resonator and the 50-ohm transmission line. Direct results of this mismatching are increased noise; shifts in the position of the baseline; and a high probability of overdriving the signal preamplifier with consequent loss of the EPR signal. We therefore designed, built, and tested a new surface-coil resonator using varactor diodes for tuning the resonance frequency to the fixed frequency oscillator and for capacitive matching of the resonator to the 50-ohm transmission line. The performance of the automatic matching system was tested in vivo by measuring EPR spectra of lithium phthalocyanine implanted in rats. Stability and sensitivity of the spectrometer were evaluated by measuring EPR spectra with and without the use of the automatic matching system. The overall experimental performance of the spectrometer was found to significantly improve during in vivo experiments using the automatic matching system. Excellent matching between the 50-ohm transmission line and the resonator was maintained under all experimental circumstances that were tested. This should allow us now to carry out experiments that previously were not possible.

Low noise CMOS readout for CdZnTe detector arrays

A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 μm low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing function incorporated in the shaper provides low power and reduces chip area. The system is partitioned into a chip containing the charge amplifiers and a chip containing the semi-Gaussian pulse shaper and multiplexer. This architecture minimizes coupling from multiplexer switches as well as shaper output to the input of the charge sensitive preamplifiers.