Abstract

The work deals with calculations for and experimental results measured on a silicon drift detector having a p-type JFET integrated in its anode. A new device design and processing steps are presented based on the self-alignment of the transistor gate to the source and drain regions. The gate is formed by drive-in of phosphorus atoms from the deposited, implanted and patterned polysilicon overlayer. The accurate matching of the anode geometrical capacitance, as calculated from computer models, to the transistor capacitance is another feature of the our detector. Such improvements made possible a measured total anode capacitance of 140 fF and at the same time a transistor transconductance of 0.22 mS at room temperature.

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