Abstract
New passive capacitor mismatch error-averaging techniques for pipelined analog-to-digital conversion is presented. The excellent linearity inherent to the architecture effectively eliminates the capacitor matching requirement that prevents a conventional monolithic pipelined analog-to-digital converter from reaching a 10-bit and above integral nonlinearity (INL) without trimming and/or calibration. Simulation results confirm the observation and a case of 14 bit INL realized by 7 bit capacitor matching is shown. The relaxed matching requirement enables the scale-down of the capacitor sizes to that of the KT/C limit. As a result, great reductions in both power consumption and chip area can be achieved.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
