Memory Margin Research Articles

The non‐essential‐essential worker: Thinking with Collins's “Revaluing work after COVID‐19”

AbstractAs I read “Revaluing Work after COVID‐19” (Collins, this issue), I wondered how was it that garment workers making the personal protective equipment (PPE) so desperately needed during the pandemic were never considered “essential workers.” As governments wrestled with the need to sustain their economies while safeguarding the health of citizens, keeping health infrastructures functioning, and ensuring the basic needs of populations could be met, they had to determine whose work was “essential.” As Collins (this issue) shows, these debates exceeded the “narrow technical meanings coming to signify workers who were putting their lives on the line to insure the well‐being of the rest of us.” Amidst celebrations of other “essential workers” and craftivists sewing masks from the comfort of their homes, the non‐essential essential labor of garment workers stayed on the margins of the historical memory of COVID‐19. This essay thinks with Collins to consider how garment workers got lost in between the scales of the national and transnational.

The Black Hole

The Black Hole Richard Bell (bio) Joshua D. Rothman,The Ledger and the Chain: How Domestic Slave Traders Shaped America. New York: Basic Books, 2021, 512 pp. Figures, notes, index. $35.00. 1315 Duke Street is about two blocks down from the UPS store in Alexandria, Virginia, on a stretch of sidewalk studded with attorneys’ offices and massage places. It’s a handsome townhouse, three stories tall and gable-roofed, its brick-work painted gun-metal grey. When John Armfield started leasing the place in 1829, it had done nearly two decades’ service as a residential dwelling—a nice place to raise a family. But Armfield ripped out its guts and renovated, turning a parlor into a meeting room for suppliers and customers. He kept the merchandise that he bought and sold at the side of the property in two high-walled yards, each one much larger than the footprint of the house itself. From Duke Street, the contents of those yards could be neither seen nor heard. But everyone knew what was kept back there. It wasn’t a secret. Arm-field wanted people to know. Soon after moving in, he installed a large sign emblazoned with his name and the name of his even better-known business partner, Isaac Franklin, above the front door. In Alexandria, everyone knew the sort of business they were in. 1315 Duke Street was a slave pen, the Virginia headquarters of the most ravenous slave trading firm anywhere in the United States. The merchandise stored in this depot and detention center were men, women, and children—dozens and dozens of them caged together on any given afternoon. Today, the visible traces of all that went on in that parlor and behind the bolted, double-locked gates to the two side yards are easy to miss. The small history museum it now houses was closed during the pandemic, and has only recently reopened. An unobtrusive historic marker, flush to the wall of the townhouse and obscured by trees, struggles for the attention of any passers-by. But foot traffic is slow these days on this section of Duke Street, which is a fifteen-minute walk from Old Town, a bustling cluster of waterfront stores that trade on their ties to George Washington and to nearby Mount Vernon. In 1829, Alexandria’s tax assessor scribbled a note to himself in the margins of a ledger describing 1315 Duke Street as “Franklin’s black hole.” It was this man’s private, personal way of marking the horrors of what happened there. [End Page 361] It’s also an apt allusion to the memory hole into which the dealings of Franklin & Armfield and the broader operations of the domestic slave trade have fallen. In antebellum America, the firm had been renowned, if not esteemed, and the massive forced migration to which it contributed—one of the largest in world history—was impossible to ignore. In the decades between 1800 and 1860, traders like John Armfield and Isaac Franklin sold at least one million enslaved people across state lines within the United States, a Second Middle Passage more than twice the size of the first. For the past century and a half, however, this domestic slave trade has lingered somewhere out of sight, confined to the darkest corners of public memory. Hardly invisible but somehow overlooked and unseen, the interstate traffic has for too long been obscured from the public eye by the shadow of the better-known transatlantic slave trade and by the seemingly insular and static regimes of plantation slavery. This didn’t happen wholly by accident. The domestic slave trade didn’t stumble into this black hole of historical forgetting by happenstance. It was pushed. In fact, people have been pushing the domestic slave trade to the margins of memory for decades. Almost every slaveowner bought or sold another human being at some point in their lives. Yet, as Robert H. Gudmestad demonstrated in A Troublesome Commerce (2003), planters in both the Upper and Lower South publicly denied their fundamental dependence on nightmare men like Franklin and Armfield, promoting instead paternalistic fantasies of benevolent mastery in which no one undeserving was ever sold away. The...

Italian trans geographies: retracing trans/cultural narratives of people and places

ABSTRACT This article maps an overlooked cultural history of Italy by exploring the literary notion of ‘trans geographies’ – a subgenre at the crossroads of autobiography, memoir, and travel narrative – through the memorialist work of sociologist and trans activist Porpora Marcasciano. Her narratives of people and place have repositioned trans identities within public spaces, while illustrating a larger phenomenon that remains underexplored within Italian Studies, namely, how places have shaped trans identities and how trans identities have, in turn, (re)shaped places. This article situates Marcasciano’s stories of gender self-determination in relation to: (1) interdisciplinary approaches to trans geographies; and (2) the writings of two very different Italian LGBT+ icons, Romina Cecconi and Mario Mieli. As a bard of the trans movement, Marcasciano has narrated concealed trans/cultural landscapes across the Italian peninsula, including Naples and the centuries-old culture of the femminielli; Rome’s dolce vita during the 1970s and 1980s; and the achievements of the trans movement in Bologna during the 1980s and the 1990s. This remapping ultimately unveils subaltern spaces that have remained at the margins of Italian collective memory as well as spaces where trans people have successfully explored new modes of inhabiting and sharing places, beyond taken-for-granted notions of normativity and transgression. The goal of this article is to outline how Marcasciano’s trans geographies have generated creative and critical sites while fostering more inclusive ways of narrating and sharing cultural history.

Solution‐Processed Dual Gate Ferroelectric–Ferroelectric Organic Polymer Field‐Effect Transistor for the Multibit Nonvolatile Memory

AbstractThe stable multibit storage operation of solution‐processed organic nonvolatile memories (ONVMs) based on ferroelectric field‐effect transistors (FeFETs) for high density data storage devices are demonstrated. The proposed multibit ONVM structure consists of a p‐type polymer semiconductor sandwiched between poly(vinylidene fluoride‐trifluoroethylene) [P(VDF‐TrFE)] layers serving as ferroelectric gate insulators to form a dual gate ferroelectric–ferroelectric memory transistor (DG Fe‐FeMT). With the extra memory space created by the spatially separated ferroelectrics, a 2‐bit memory representation (“11”, “10”, “01” and “00”) with clear memory margins is achieved due to the bistability of each P(VDF‐TrFE) and the high performance of the polymer semiconductor. The distinct four‐level reading of memory output currents (IM,OUTs) results from the independent programming voltages of the dual gates. An excellent distinct six‐levelIM,OUTsare also achieved in DG Fe‐FeMT using the intermediate programming voltages. Finally, the possibility of 3−bit, or 8 memory states, are demonstrated by optimizing the bistability and intermediate polarization states of the ferroelectrics without increasing the device area horizontally. The DG Fe‐FeMT has a great potential for cost−effective flexible nonvolatile multibit data storage devices due to its solution‐process and low annealing temperatures.

Characterization of nanoscale vertical-channel charge-trap memory thin film transistors using oxide semiconducting active and trap layers

We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In–Ga–Zn–O channel and ZnO charge trap layers, in which a solution-processed SiO2 spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 × 105 and 5.1 × 102 with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 104 s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2.

Design of n+-base width of two-terminal-electrode vertical thyristor for cross-point memory cell without selector

The n+-base width of a two-terminal vertical thyristor fabricated with n++(top-emitter)-p+(base)-n+(base)-p++(bottom-emitter) epitaxial Si layers was designed to produce a cross-point memory cell without a selector. Both the latch-up and latch-down voltages increased linearly with the n+-base width, but the voltage increase slope of the latch-up was 2.6 times higher than that of the latch-down, and the memory window increased linearly with the n+-base width. There was an optimal n+-base width that satisfied cross-point memory cell operation; i.e. ∼180 nm, determined by confirming that the memory window principally determined the condition of operation as a cross-point memory cell (i.e. one half of the latch-up voltage being less than the latch-down voltage and a sufficient voltage difference existing between the latch-up and latch-down voltages). The vertical thyristor designed with the optimal n+-base width produced write/erase endurance cycles of ∼109 by sustaining a memory margin (I on /I off ) of 102, and the cross-point memory cell array size of 1024 K sustained a sensing margin of 99 %, which is comparable with that of current dynamic random-access memory (DRAM). In addition, in the cross-point memory cell array, a ½ bias scheme (i.e. a memory array size of 1024 K for 0.02 W of power consumption) resulted in lower power consumption than a bias scheme (i.e. a memory array size of 256 K for 0.02 W of power consumption).

Impact of oxide gate electrode for ferroelectric field-effect transistors with metal-ferroelectric-metal-insulator-semiconductor gate stack using undoped HfO2 thin films prepared by atomic layer deposition

Ferroelectric field-effect transistors (FETs) with a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) gate stack were fabricated and characterized to elucidate the key process parameters and to optimize the process conditions for guaranteeing nonvolatile memory operations of the device when the undoped HfO2 was employed as ferroelectric gate insulator. The impacts of top gate (TG) for the MFM part on the memory operations of the MFMIS-FETs were intensively investigated when the TG was chosen as metal Pt or oxide ITO electrode. The ferroelectric memory window of the MFMIS-FETs with ITO/HfO2/TiN/SiO2/Si gate stack increased to 3.8 V by properly modulating the areal ratio between two MFM and MIS capacitors. The memory margin as high as 104 was obtained during on- and off-program operations with a program pulse duration as short as 1 μs. There was not any marked degradation in the obtained memory margin even after a lapse of retention time of 104 s at 85 °C and repeated program cycles of 10,000. These obtained improvements in memory operations resulted from the fact that the choice of ITO TG could provide effective capping effects and passivate the interfaces.

Forming-Free Cu-Doped Amorphous-Carbon-Oxide Based Resistive-Random-Access-Memory and Memory Operation Mechanism

Recently, the demand for more data storage and fast processing has been dramatically increased for the big data markets such as artificial intelligence (AI), virtual reality (VR), autonomous car, and internet of things (IoT). Thus, a new memory such as a storage class memory (SCM) has been introduced since it can perform a reasonable latency compared to DRAM and a lower bit-cost than NAND flash memory [1]. Remind that, generally, a SCM has been fabricated with three-dimensional cross point memory cell array [2]. As a candidate memory cell for SCM, resistive-random-access-memory (ReRAM) has been proposed; i.e., called storage-type SCM. Santini, C. A. et al. demonstrated amorphous carbon oxide (a-COx) based ReRAM-cell having a reasonable memory window margin (I on/I off > 100), a fast switching speed of 20~50 ns at ~ 100-nm-diameter memory cell size. However, it showed extremely a high forming voltage (V forming) of ~ 5.0 V and a high reset voltage (V reset) of ~ – 4.0 V [3]. In particular, the a-COx based ReRAM-cell presented a different bi-stable memory characteristic for another typical ReRAM-cells; i.e., its bias directions of set and reset were opposite to a typical ReRAM, which mechanism was not evidently proved. In addition, the forming process for this ReRAM cell would be highly undesirable since it caused an extra burden for initializing memory-cells and degraded the write and erase endurance cycles [4].Here, for the first time, we designed a forming-free Cu-doped amorphous-carbon-oxide based ReRAM cell, which did not need a forming process and we reviewed the memory operation mechanism by understanding electrical and chemical properties of the Cu-doped a-COx based ReRAM cells. A typical a-COx based ReRAM-cell needed a forming process; i.e., a forming voltage of – 2.20 V and a set voltage of – 1.05 V, as shown in Fig. 1 (a). Otherwise, a Cu-doped a-COx based ReRAM-cell could achieve a forming-free process; i.e., a forming voltage (i.e. - 0.85 V) was the same as a set voltage (i.e. – 0.85 V), as shown in Fig. 1 (b). In addition, it demonstrated a write and erase endurance cycles of ~106 by sustaining a memory margin of ~1.3×102, being able to be utilized for a commercial nonvolatile memory-cell, as shown in Fig. 1(c). To clarify the forming-free mechanism, the depth profiles of C, Cu, and O atom in the Cu-doped a-COx memory cell were observed in detail under pristine, after set, and after reset process, which were obtained from intensity line-profiles of EELS/EDS elemental mapping images at C-K edges, O-K edges, Cu-Kα, Pt-La1, and W-La1. For the pristine state, C, Cu, and O atoms are uniformly distributed in the Cu-doped a-COx layer, as shown in Fig. 1(d). In addition, after a set process, since a negative voltage was applied to the top Pt electrode, Cu atoms evidently moved and segregated toward the top Pt electrode, as shown in a of Fig. 1(e), while O atoms evidently migrated and pile up toward the bottom W electrode, as shown in b of Fig. 1(e). This result means that the conductive C-C sp2 filaments in the Cu-doped a-COx layer were produced when oxygen atoms migrated and piled up toward bottom W electrode and the conductive Cu-atom filaments were formed in the Cu-doped a-COx layer since Cu atom moved and segregated toward the top Pt electrode. Hence, both conductive C-C sp2 filaments and Cu-atom filaments were generated simultaneously in the Cu-doped a-COx layer, achieving a set process without a forming process. On the other hand, after a reset process, since a positive voltage was applied to the top Pt electrode, Cu and O atoms were redistributed inside the Cu-doped a-COx, resulting in breaking both C-C sp2 filaments and Cu-atom filaments, as shown in a and b of Fig. 1(f). In our presentation, we will demonstrate and review the mechanisms between a set process without forming process and a reset process in detail by electrical and chemical composition depth profiles depending on the applied bias condition. In particular, we will demonstrate a different ReRAM behavior of the Cu-doped a-COx based ReRAM from a typical ReRAM or CBRAM. Acknowledgement This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Reference [1] Matsui, C. et al. Integration 2019, 69, 62-74.[2] Hady, F. T. et al. Proceedings of the IEEE 2017, 105, (9), 1822-1833.[3] Santini, C. A. et al. Nature Communications 2015, 6, (1), 8600.[4] Skaja, K. et al. Scientific Reports 2018, 8. Figure 1

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.0 V at a VGS sweep of ±20 V and a large memory margin of 1.6 × 102 at a program pulse duration as short as 5 ms. The programmed memory margin higher than 105 did not experience any degradation with time evolution for 104 s. The mechanical durability was also evaluated after the delamination process of polyimide (PI) film. There were no marked variations in charge-trap-assisted MW even at a curvature radius of 1 mm and programmed memory margin even after repeated program operations of 104 cycles. The introduction of ALD process for the formation of IGZO active channel was suggested as a main process parameter to ensure the excellent memory device characteristics of the V-CTM TFTs.

The Enigma of Arthur Griffith: 'Father of Us All' by Colum Kenny (review)

Reviews The Enigma of Arthur Griffith: ‘Father of Us All’, Colum Kenny (Newbridge, Co. Kildare: Merrion Press, 2020), 323 pages. Just inside the entrance to Leinster House hang imposing portraits of seminal figures from the history of Ireland’s long and often bitter struggle for freedom from the cosh of British imperialism and the baleful consequences of colonisation. It is not necessary to be a history buff to quickly recognise the names and faces of Robert Emmett, W T Cosgrave or Michael Collins, but the face of Arthur Griffith is more likely than not to provoke a vaguer response. Yet Griffith is the man whom Collins insisted was the ‘Father of us all’, a glowing accolade from a credible source and one that makes its way into the subtitle of Colum Kenny’s fascinating biography of Griffith. Not yet a century dead, after a life lived right at the heart of the maelstrom of the events leading to partition and the foundation of ‘the Free State’, and indeed often in the driving seat, it seems odd that Griffith’s memory has faded so quickly while other names have found a fixed, if disputed, place in the firmament of founding heroes. If this book is about anything it is about the placing of Griffith high in that firmament. The main title of the book, The Enigma of Arthur Griffith, suggests that perhaps the answer to public disregard of Griffith lies in Griffith himself. Was he an enigmatic person, mysterious and difficult to comprehend? As Kenny unfolds the Griffith narrative, it becomes clear that the real enigma is not Griffith at all but the fact of his consignment to the margins of memory. Certainly, by the end of this meticulously researched biography Griffith himself is no enigma. Rather, his life and times, his context, persona, principles and perceptions are laid bare. Stripped away, too, are layers of misunderstanding, clouded judgement, skewed analysis and misrepresentation which have done Griffith’s memory no favours. By the end, it is possible to see that Collins’s powerful accolade was laid on deserving shoulders. Griffith lived in times of political high drama, his life an endless swirl of associations and friendships with the entire cast of legendary names that brought Ireland out of the doldrums and on the pathway to the modern world. He took no active part in the Rising, but he was no mere spectator. A man of action and ideas, who drove the debate, his writings, his ideas and principles, are both warp and weft in the rough fabric of that watershed time in Irish history. He was the Studies • volume 109 • number 434 237 Summer 2020: Book Reviews founder of Sinn Féin, President of Dáil Éireann and, crucially, chairman of the team which negotiated the 1921 Anglo-Irish Treaty. He was destined to be the man who carried the blame for partition in many eyes but, as Colum Kenny points out early on, the Northern Ireland Parliament was already up and running when the Treaty negotiations commenced. I sometimes walk past the house in which Griffith and his wife and children lived in Clontarf, and which remembers him in a simple plaque at the front door. It reads: ‘From 1911 until his death in 1922 this was the home of Arthur Griffith, Patriot and Statesman. His Monument. An Ireland Free’. Left to his own devices, it is unlikely he would ever have owned his own home, for the workaholic artisan printer turned writer, editor, polemicist, politician, did not know the meaning of rest or personal reward when it came to promoting the cause of Irish freedom. He was one of Dublin’s poor who, by his own innate curiosity and genius, made of himself a self-educated intellectual who could hold his own and shine in any company in the arts, music, politics and the pub. He never earned enough to buy the house in Clontarf. Instead, his friends and supporters took up a collection after he married and bought the house for him. The list of contributors tells its own story of how highly he was regarded. Look at some of the names among the two hundred and fifty...

Improvement in Long-Term and High-Temperature Retention Stability of Ferroelectric Field-Effect Memory Transistors With Metal–Ferroelectric–Metal–Insulator–Semiconductor Gate-Stacks Using Al-Doped HfO2 Thin Films

Nonvolatile memory characteristics of the ferroelectric field-effect transistors (FeFETs) were investigated by introducing the metal–ferroelectric–metal–insulator–semiconductor (MFMIS) gate-stacks, employing Al-doped HfO2 (Al:HfO2) ferroelectric thin films. The obtained memory window (MW) of the MFMIS FETs increased from 1.0 to 2.8 V by increasing the areal ratios of the metal–insulator–semiconductor (MIS) to the metal–ferroelectric–metal (MFM) (SI/SF) from 8 to 32. The device with an SI/SF ratio of 16 exhibited a 3-order-of-magnitude on/off memory margin even with a program pulse duration of 500 ns. The long-term data retention was also verified by improving the tolerance against the depolarization field by introducing the MFMIS gate-stacks, which can use fully saturated polarization. The temperature-dependent memory performance and operational reliabilities of the MFMIS-FETs were also investigated at high temperatures to exploit fully the thermal stability of the Al:HfO2. The obtained MWs were not markedly degraded for a retention time of 104 s from room temperature (RT) to 80 °C.

Multi-level operation of three-dimensionally stacked non-volatile ferroelectric polymer memory with high-performance hole-injection layer

Abstract Carrier injection from the source electrode to the semiconducting channel in a field-effect transistor (FET) is efficiently enhanced by inserting an interlayer capable of reducing the injection barrier, yielding a device with a greatly increased ON current. In this study, we demonstrated a non-volatile vertical-channel (VC) ferroelectric field effect transistor (FeFET) memory based on ferroelectric polarization switching of a ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as a gate insulator with a thin MoO3 interlayer. Owing to the facile hole injection through the MoO3 interlayer to a semiconducting channel of the FeFET, the saturated ON current was significantly increased, giving rise to a large ON/OFF memory margin. Optimization of the VC-FeFET thus led to a non-volatile memory operating at a programming voltage of ±25 V with a maximum ON/OFF current margin of 103, reliable time-dependent data retention for more than 1 year, and write/erase endurance for 105 cycles. Furthermore, by sequentially stacking three arrays of VC-FeFETs with the hole-injection interlayers, we fabricated three-dimensionally (3D) stacked VC-FeFETs. Each device had a sufficient ON/OFF current ratio for multi-level memory operation, in which four distinct states were repetitively programmed and erased with long-term data retention and reliable cycle endurance.

Characterization on the operation stability of mechanically flexible memory thin-film transistors using engineered ZnO charge-trap layers

The charge-trap memory thin-film transistors (CTM-TFTs) using ZnO charge-trap layer (CTL) were fabricated and characterized, in which ZnO CTL was deposited by atomic layer deposition (ALD) and the deposition temperatures were controlled to be 75, 100, and 125 °C to improve both specifications of device characteristics and stability for the flexible memory devices. The CTM-TFT using ZnO CTL deposited at 100 °C obtained a wide memory window (MW) of 14.7 V, large memory margin between ON- and OFF-states (ION/IOFF, 7.3 × 106) at 1 µs voltage pulses. The ION/IOFF larger than 107 was also obtained with a progress of retention time. It was noteworthy that the deposition temperature for the ZnO CTL was worked as one of the most important control parameters affecting the memory device characteristics of the fabricated flexible CTM-TFTs. Alternatively, the fast program operation and long retention time were suggested to result from a suitable number of trap sites and their appropriate positions within the ZnO CTL prepared at 100 °C. The improved device stabilities were guaranteed even under bending condition at a radius of curvature of 10 mm after the delamination process of PI film substrate from carrier glass.

Study on Forming-Free Characteristic of Amorphous Carbon Oxide Reram By Controlling Cu-Filament Shape

Resistive random access memory (ReRAM) is one of the most promising candidates for the next-generation memory due to its simple structure, high switching speed and low power consumption [1]. Recently, there has been large interests in using carbon-baed material as solid electrolyte to overcome the limit of conventional metal-oxide memory. It has remarkable advantages over past metal-oxide memory such as high memory margin (Ion/Ioff > 100) and fast switching speed (20~50ns) [2]. However, the requirement of forming process to activate resisitive switching operation is one of the critical issues. Forming process may degrade the device switching characteristic and is not desirable for circuit design. In this study, forming-free characteristic of a-COx (amorphous carbon oxide) based ReRAM was observed by controlling the Cu-filament shape. To accurately control the Cu-atom concentration profile, insertion of Cu thin film was carried out in several ways. The first device, named A, was fabricated with the common ReRAM structure of Pt / Cu-doped a-COx / W. The second device, named B, was vertically stacked with the strcutrue of Pt / a-COx / Cu-doped a-COx / W. The third device, named C, was vertically stacked with the strcutrue of Pt / Cu-doped a-COx / a-COx / Cu-doped a-COx / W. The device was fabricated on W bottom electrode wafer patterned from 34 nm to 1921 nm by photo lithography process. The a-COx and other metals were deposited using dc magnetron sputter (PVD method). After the fabrication, the Cu-atom concentration profile was carefully examined using SIMS analysis to understand the correlation between forming-free chracteristic and Cu-filament shape. Forming-free characteristic device presented identical forming and set voltage of -0.85 V. Moreover, the result indicated that the high resistance state current of 2.41-7 A at 0.1 V, low resistance state current of 5.98-5 A at 0.1 V and the memory window margin (Ion/Ioff) of 2.48×102. In our study, we present that the precise design of the Cu-atom concentration profile of a-COx based ReRAM is the significant key to achieve the forming-free and stable non-volatile memory characteristic. [1] Daniele Ielmini, Semicond. Sci. Technol. 31 (2016) 063002 [2] Claudia A. Santini et al, NAT COMMUN, 6:8600 (2015) * This material is based upon work supported by the Ministry of Trade, Industry & Energy(MOTIE, Korea) under Industrial Technology Innovation Program (10068055). Figure 1

Refugees at the Margins: Jewish Domestics in Britain 1938–1945

From shortly after the Anschluss until the beginning of the Second World War, about twenty thousand Jewish refugees were admitted to Britain as live-in domestic servants in British homes. These women (and a few men) comprised about one-third of all Jewish refugees admitted into Britain in the 1930s, but unlike prominent scientists and intellectuals or the Kindertransportees, they have remained at the margins of British public memory of the 1930s. However, hundreds of these former refugee domestics have left testimonies and memoirs that narrate their experiences before, during, and after the war including their reception by Anglo-Jews and non-Jews, and their experiences of alienation, belonging, adjustment, and loss. This paper examines these testimonies to find commonalities in Jewish refugee domestics' pre-emigration and refugee lives and argues that the very terms under which they were allowed to come to the United Kingdom as well as the limits of testimony-giving have perpetuated their marginalization and absence from Jewish refugee and wartime social histories.

Demonstration of α-InGaZnO TFT Nonvolatile Memory Using TiAlO Charge Trapping Layer

Amorphous indium gallium zinc oxide (α-InGaZnO) thin-film transistors using as nonvolatile memories (TFT-NVMs) with an Al2O3/TiAlO/Al2O3 charge trapping engineered structure have been demonstrated experimentally at low thermal budget of 300 °C. The high- k composite TiAlO layer with a high trap state density and a high dielectric constant was prepared by sputtering at room temperature as a charge trapping material. According to the high-resolution transmission electron microscopy analyses, the Al2O3/TiAlO/Al2O3 gate stack exhibited sharp interfaces and a uniform distribution of Ti and Al elements in the TiAlO film. The programming and retention characteristics of the fabricated α-InGaZnO TFT-NVMs were investigated in detail. The TFT-NVMs exhibited excellent programming characteristics with a large memory window of around 5.74 V under a 16 V programming voltage. It can also maintain a memory margin of about 5 V after 10 years, indicating only ∼15% charge loss. This paper suggests that α-InGaZnO TFT-NVMs using the high- k TiAlO composite material as the charge trapping material are promising for future nonvolatile memories applications in display technology, flexible and wearable electronics.

Memristive devices with a large memory margin based on nanocrystalline organic-inorganic hybrid CH3NH3PbBr3 perovskite active layer

Abstract Perovskite materials have been utilized as promising active materials for memristive devices due to their excellent properties. However, most reported perovskite-based memristive devices exhibit relatively low current ON/OFF ratios, which limits their practical applications in memory devices. In this work, memristive devices with a large memory margin were fabricated utilizing a CH3NH3PbBr3 (MAPbBr3) perovskite layer. The nanocrystalline MAPbBr3 perovskite thin films were successfully formed at low temperature by using a chlorobenzene dripping method. The MAPbBr3 perovskite layer was employed as a resistive switching layer in memristive devices with a structure of indium-tin-oxide/poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate)/MAPbBr3/Al. The maximum ON/OFF ratio of the memristive devices based on the MAPbBr3 perovskite was as large as 3.6ｘ106. The memristive devices showed high device-to-device reproducibility with set-voltage distributions between −0.5 and −0.8 V, as well as good endurances of at least 120 cycles and retention times longer than 1ｘ104 s. The carrier transport mechanisms of the memristive devices were described on the basis of the I-V curves, and their operating mechanisms were explained via the formation and rupture of filaments in the MAPbBr3 perovskite.

Effect of Misfit Dislocations in Junctions and Base Thickness on Latch-up Characteristics in Two-Terminal Vertical Thyristor-Based Capacitorless Memory

Conventional dynamic random access memory (DRAM) has been facing a severe challenge to scale down to 10 nm size. The cell capacitor should be able to store sufficient charges of 25~30 fF/cell. In order to meet this requirement, high aspect ratio of cell capacitor is inevitable, resulting in capacitors leaning into each other. To overcome this issue coming from capacitor, the vertical thyristor-based two-terminal capacitorless memory was proposed as a promising candidate to replace current DRAM, which consists of p++-anode / n+-base / p+-base / n++-cathode vertical structure using conventional Si technology. The two-terminal vertical thyristor-based capacitorless memory cell having p++-anode / n+-base / p+-base / n++-cathode vertical structure is easy to construct cross-point memory array cells, as shown in Figure 1. Furthermore, Two-terminal vertical thyristor-based capacitorless memory array cells can be operated without selector since sneak current is suppressed by latch-down process. In our study, three types of two-terminal vertical thyristor-based capacitorless memory cells consist of top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 80-nm-thick base region (PNPN80), top-p++-anode / n+-base / p+-base / bottom-n++-cathode with 160-nm-thick base region (PNPN160), and top-n++-cathode / p+-base / n+-base / bottom-p++-anode with 160-nm-thick base region (NPNP160) were fabricated, individually. The dopant concentration profile of each device was analyzed by secondary ion mass spectroscopy (SIMS), as shown in Figure 2. By correlating HR TEM images with SIMS analyses, misfit dislocations were observed at the depth where dopant pile-up was found, as shown in Figure 3. Figure 4 (a), (b) and (c) show I-V measurements of PNPN80, PNPN160 and NPNP160, respectively. The difference of latch-up voltages between Figure 4 (b) and (c) can be explained by carrier life-time difference. NPNP160 had less misfit dislocations compared to PNPN160, resulting in longer excess carrier life-time, since dislocations act as recombination centers. Thus, NPNP160 needed smaller anode voltage to induce sufficient excess carriers in base regions, which had smaller latch-up voltage than PNPN160. In addition, the difference of latch-up voltages between Figure 4 (a) and (b) resulting from base thickness difference can be explained by electric field. The electric field of PNPN160 is weaker than that of PNPN80 in base regions when equivalent anode voltage is applied. Therefore, PNPN160 needed larger anode voltage to lower the injection barrier of excess carriers. Besides, the effect of misfit dislocations and base dopant concentration on memory margin and off-state leakage current will be discussed. Finally, the memory cell pulse operations will be exhibited as well. Acknowledgment * This research was supported by Brain Korea 21 PLUS Program in 2018, the MOTIE (Ministry of Trade, Industry & Energy 10069063) and KSRC (Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. Figure 1

Design of Double Pinned Perpendicular Magnetic-Tunnel-Junction Spin-Valve Exhibiting Multiple Resistance States

Perpendicular spin-transfer-torque magnetic random access memory (p-STT MRAM) cells consist of a perpendicular magnetic tunnel junction and a selective device has been researched intensively because of the possibility of overcoming the scaling limitations of the current dynamic random access memory (DRAM) below the 10-nm design rule [1]. p-STT-MRAM requires high tunneling magnetoresistance (TMR) ratio greater than 150%, sufficient thermal stability (Δ=KuV/kBT) above 75 for a ten-year retention-time, and low switching current (J C0 ~ 1 MA/cm2) must be achieved for low power consumption [2-3]. However, the thermal stability is hard to maintain when scaling down in 10-nm scale of the p-STT MRAM cells for terabit integration. It requires high interfacial anisotropy K i to maintain the thermal stability requirement for 10-year retention time [4]. In this study, we designed a p-MTJ spin-valve with a double pinned structure to realize two-bit operation to secure a larger scaling limit (see Fig. 1(a)). We investigated the dependency of the number of [Co/Pt]n multilayers on the coupling strength to the pinned layers in order to control the spin-electron direction of the pinned layers. The total number of [Co/Pt]n SyAF multilayers ferro-coupled to the bottom pinned layer was reduced from 9 to 3 layers to reduce the roughness of the MgO tunneling barrier to increase the TMR ratio. Also, the number of [Co/Pt]n of the top upper SyAF multilayers was modulated so that the coercive field (H c) required to switch the spin-electron direction of the top pinned layer increased from about 0.3 kOe to 1 kOe which is sufficient to ensure the memory margin for two-bit operation, as shown in Fig. 1(b). Then, we investigated the multiple resistance states with the R-H loop of the double pinned p-MTJ spin-valve, as shown in Fig. 1(c). It showed four different resistance states depending on the spin-electron direction of the free layers and pinned layers as shown in Fig. 1(d) with a maximum TMR ratio of 166%. This implies that the double pinned p-MTJ spin-valve may be suitable for terabit integration compared to that of the single-bit operating p-STT MRAM memory cells. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2017R1A2A1A05001285) and Brain Korea 21 PLUS Program in 2014.

Enlarged memory margins for resistive switching devices based on polyurethane film due to embedded Ag nanoparticles

Current-voltage (I-V) properties of indium-tin-oxide/Ag nanoparticles embedded in polyurethane film/Al devices exhibited a current bistability with ON/OFF ratio within the range of 105–103 with the variation of voltage from −0.85 to 3.95 V, which was nearly 102 larger than that for the device without Ag nanoparticles. The memory margin was obviously enlarged due to the existence of the Ag nanoparticles embedded in the polyurethane layer. I-V properties and write-read-erase-read voltage cycles test indicated the flash resistive switching properties. The data retention time reach up to 1.8 × 104 s, which manifested the stability of the memory devices. I-V property at ON state was attributed to the drift mechanism, and the property at OFF state was related to the space-charge-limited-current behaviors.