Design of Double Pinned Perpendicular Magnetic-Tunnel-Junction Spin-Valve Exhibiting Multiple Resistance States

Abstract

Perpendicular spin-transfer-torque magnetic random access memory (p-STT MRAM) cells consist of a perpendicular magnetic tunnel junction and a selective device has been researched intensively because of the possibility of overcoming the scaling limitations of the current dynamic random access memory (DRAM) below the 10-nm design rule [1]. p-STT-MRAM requires high tunneling magnetoresistance (TMR) ratio greater than 150%, sufficient thermal stability (Δ=KuV/kBT) above 75 for a ten-year retention-time, and low switching current (J C0 ~ 1 MA/cm2) must be achieved for low power consumption [2-3]. However, the thermal stability is hard to maintain when scaling down in 10-nm scale of the p-STT MRAM cells for terabit integration. It requires high interfacial anisotropy K i to maintain the thermal stability requirement for 10-year retention time [4]. In this study, we designed a p-MTJ spin-valve with a double pinned structure to realize two-bit operation to secure a larger scaling limit (see Fig. 1(a)). We investigated the dependency of the number of [Co/Pt]n multilayers on the coupling strength to the pinned layers in order to control the spin-electron direction of the pinned layers. The total number of [Co/Pt]n SyAF multilayers ferro-coupled to the bottom pinned layer was reduced from 9 to 3 layers to reduce the roughness of the MgO tunneling barrier to increase the TMR ratio. Also, the number of [Co/Pt]n of the top upper SyAF multilayers was modulated so that the coercive field (H c) required to switch the spin-electron direction of the top pinned layer increased from about 0.3 kOe to 1 kOe which is sufficient to ensure the memory margin for two-bit operation, as shown in Fig. 1(b). Then, we investigated the multiple resistance states with the R-H loop of the double pinned p-MTJ spin-valve, as shown in Fig. 1(c). It showed four different resistance states depending on the spin-electron direction of the free layers and pinned layers as shown in Fig. 1(d) with a maximum TMR ratio of 166%. This implies that the double pinned p-MTJ spin-valve may be suitable for terabit integration compared to that of the single-bit operating p-STT MRAM memory cells. Acknowledgements This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2017R1A2A1A05001285) and Brain Korea 21 PLUS Program in 2014.