Heuristic Mapping Research Articles

Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip

Application mapping in 2-D mesh-based Network-on-Chip (NoC) architecture is an optimization problem in which each application task (e.g., processor or memory units) should be mapped one-to-one onto a network element (switch or router) to optimize performance requirements (e.g., communication energy or communication latency) under certain platform constraints (e.g., bandwidth and/or latency). Network-on-Chip is a scheme that establishes links between limited application-specific components within Multi-Processor System-on-Chip (MPSoC), but it has a vital role to ensure the maximum data transfer rate and reduce total number of physical interconnections. Most of the works on heuristic application mapping for mesh-based NoC design aim to minimize both total communication energy and run-time, however they experience the following issues: (i) relatively high CPU time due to linear search for the task and tile mapping combinations, (ii) consumption of relatively high communication energy due to random tile selection when two or more tiles are equivalent in terms of average weighted distance by their adjacent mapped tasks, and (iii) even after constructive application mapping, some of the tasks consume higher communication energy due to their inappropriate placements. In this paper we present a low time-complexity heuristic mapping algorithm of weighted application graph under permissible bandwidth constraint to minimize communication energy of 2-D mesh-based NoC architecture. The experimental results of multimedia benchmarks, as well as randomly generated samples show the low communication energy as well as time-complexity under bandwidth constraints in comparison to the recent heuristic application mapping approaches. In our approach, the communication energy is also close to the optimal solution obtained by Integer Linear Programming (ILP).

Learning Discrete Matrix Factorization Models

Matrix factorization is among the most popular approaches for matrix completion, with recent advances including gradient-based and deep-learning-based methods. Even though many applications involve matrices with discrete values, most of the existing matrix factorization models focus on the continuous domain. Discretization is applied as an additional step, often using a heuristic mapping that results in sub-optimal solutions, which either do not take into account the structure of the matrix or introduce significant quantization errors. In this letter, we propose a novel method that allows gradient-based and deep-learning-based methods to jointly learn both the matrix factorization model and a discretization operator. By introducing a loss function that accounts for the reconstruction error with respect to the discrete predictions, we obtain a discrete matrix completion algorithm with high reconstruction accuracy. Experiments using well-known datasets show the improvement obtained by the proposed algorithm over the state of the art.

A novel reinforcement learning algorithm for virtual network embedding

Abstract Network virtualization enables the share of a physical network among multiple virtual networks. Virtual network embedding determines the effectiveness of utilization of network resources. Traditional heuristic mapping algorithms follow static procedures, thus cannot be optimized automatically, leading to sub-optimal ranking and embedding decisions. To solve this problem, we introduce a reinforcement learning method to virtual network embedding. In this paper, we design and implement a policy network based on reinforcement learning to make node mapping decisions. We use policy gradient to achieve optimization automatically by training the policy network with the historical data based on virtual network requests. To the best of our knowledge, this work is the first to utilize historical requests data to optimize network embedding automatically. The performance of the proposed embedding algorithm is evaluated in comparison with two other algorithms which use artificial rules based on node ranking. Simulation results show that our reinforcement learning is able to learn from historical requests and outperforms the other two embedding algorithms.

Stochastic and exact methods for service mapping in virtualized network infrastructures

SummaryThis paper presents a stochastic algorithm for virtual network service mapping in virtualized network infrastructures, based on reinforcement learning (RL). An exact mapping algorithm in line with the current state of the art and based on integer linear programming is proposed as well, and the performances of the two algorithms are compared. While most of the current works in literature report exact or heuristic mapping methods, the RL algorithm presented here is instead a stochastic one, based on Markov decision processes theory. The aim of the RL algorithm is to iteratively learn an efficient mapping policy, which could maximize the expected mapping reward in the long run. Based on the review of the state of the art, the paper presents a general model of the service mapping problem and the mathematical formulation of the 2 proposed strategies. The distinctive features of the 2 algorithms, their strengths, and possible drawbacks are discussed and validated by means of numeric simulations in a realistic emulated environment.

Non-uniform Illumination Video Enhancement Based on Zone System and Fusion

In daily life, the acquisition of digital video will introduce non-uniform exposure due to the set of shooting equipment or scene illumination. Due to the low visibility, details are hidden and these videos usually fail to present visually pleasing browsing. Previous work typically relies on a single heuristic tone mapping curve to expand the dynamic range, which inevitably leads to uneven exposure. To solve this problem, we present a new video enhancement method based on zone system and image fusion. Given an input non-uniform illumination video, we first apply the zone system for exposure evaluation. We then remap each region using a series of tone mapping curves to generate multi-exposure regions which contain different exposed versions. Guided by some visual perception quality measures, we locate all the best exposed regions and then integrate them into a well-exposed video frame. Finally, in order to keep temporal consistency, we temporally propagate the zone regions from the former frame to the current frame. Experimental results have shown that the enhanced video exhibits uniform exposure, and preserves temporal consistency.

CALM

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), on-chip networks are facing serious challenges in providing fast communication among various tasks and cores. One promising on-chip network design approach shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behaviors, both of which have not been fully exploited in existing mapping algorithms. In this article, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened butterfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

A heuristic multi-criteria classification approach incorporating data quality information for choropleth mapping

ABSTRACTDespite conceptual and technology advancements in cartography over the decades, choropleth map design and classification fail to address a fundamental issue: estimates that are statistically indifferent may be assigned to different classes on maps or vice versa. Recently, the class separability concept was introduced as a map classification criterion to evaluate the likelihood that estimates in two classes are statistical different. Unfortunately, choropleth maps created according to the separability criterion usually have highly unbalanced classes. To produce reasonably separable but more balanced classes, we propose a heuristic classification approach to consider not just the class separability criterion but also other classification criteria such as evenness and intra-class variability. A geovisual-analytic package was developed to support the heuristic mapping process to evaluate the trade-off between relevant criteria and to select the most preferable classification. Class break values can be adjusted to improve the performance of a classification.

Dynamic task mapping for Network-on-Chip based systems

Efficiency of Network-on-Chip (NoC) based multi-processor systems largely depends on optimal placement of tasks onto processing elements (PEs). Although number of task mapping heuristics have been proposed in literature, selecting best technique for a given environment remains a challenging problem. Keeping in view the fact that comparisons in original study of each heuristic may have been conducted using different assumptions, environment, and models. In this study, we have conducted a detailed quantitative analysis of selected dynamic task mapping heuristics under same set of assumptions, similar environment, and system models. Comparisons are conducted with varying network load, number of tasks, and network size for constantly running applications. Moreover, we propose an extension to communication-aware packing based nearest neighbor (CPNN) algorithm that attempts to reduce communication overhead among the interdependent tasks. Furthermore, we have conducted formal verification and modeling of proposed technique using high level Petri nets. The experimental results indicate that proposed mapping algorithm reduces communication cost, average hop count, and end-to-end latency as compared to CPNN especially for large mesh NoCs. Moreover, proposed scheme achieves up to 6% energy savings for smaller mesh NoCs. Further, results of formal modeling indicate that proposed model is workable and operates according to specifications.

Communication‐aware thread mapping using the translation lookaside buffer

SummaryThreads of parallel applications need to communicate in order to fulfill their tasks. The communication performance between the cores in modern multi‐core architectures differs because of the memory and interconnection hierarchies. In these architectures, it is important to map the threads of parallel applications by taking into account the communication between them, to improve their performance and energy consumption. In parallel applications based on shared memory, communication is implicit, which makes it difficult to detect the communication pattern between the threads.In this paper, we introduce a new lightweight mechanism to detect the communication pattern between threads of shared memory applications using the translation lookaside buffer. Our mechanism relies on hardware features, which make it transparent to the programmer and allow the detection to be performed by the operating system during the execution of the application. We also developed a heuristic mapping algorithm that uses the detected pattern to dynamically map the threads to cores. Experiments were performed with applications from the NAS‐OMP and PARSEC parallel benchmark suites in a simulated machine as well as a real machine. Results show that our mechanism can substantially improve parallel application performance, as well as processor and DRAM energy consumption. Copyright © 2015 John Wiley & Sons, Ltd.

A Hybrid Reliable Heuristic Mapping Method Based on Survivable Virtual Networks for Network Virtualization

The reliable mapping of virtual networks is one of the hot issues in network virtualization researches. Unlike the traditional protection mechanisms based on redundancy and recovery mechanisms, we take the solution of the survivable virtual topology routing problem for reference to ensure that the rest of the mapped virtual networks keeps connected under a single node failure condition in the substrate network, which guarantees the completeness of the virtual network and continuity of services. In order to reduce the cost of the substrate network, a hybrid reliable heuristic mapping method based on survivable virtual networks (Hybrid-RHM-SVN) is proposed. In Hybrid-RHM-SVN, we formulate the reliable mapping problem as an integer linear program. Firstly, we calculate the primary-cut set of the virtual network subgraph where the failed node has been removed. Then, we use the ant colony optimization algorithm to achieve the approximate optimal mapping. The links in primary-cut set should select a substrate path that does not pass through the substrate node corresponding to the virtual node that has been removed first. The simulation results show that the acceptance rate of virtual networks, the average revenue of mapping, and the recovery rate of virtual networks are increased compared with the existing reliable mapping algorithms, respectively.

Which ‘C’ Are You Talking About? Critical Meets Cultural IPE

This review article maps the positions of critical and cultural IPE within this diverse field. To this end, I propose a stylised analogy as a heuristic mapping device. Think of IPE as a parliamentary polity with elections at regular intervals. There is the majority group of the incumbent government, which remains confident of running things properly despite the occasional mistake; there is the parliamentary opposition, which promises to run things differently from within the established institutions; and, finally, there is the extra-parliamentary opposition, which pushes for radical change from outside the dedicated platforms for political contestation. In this analogy, orthodox IPE acts like the government majority, cultural IPE like the parliamentary opposition and critical IPE like the extra-parliamentary opposition of the discipline. Similar to political alternatives that bring about only marginal change, however, this double opposition does not fully destabilise the underpinnings of the discipline. Applying post-racist insights from the works of John M. Hobson and J. M. Blaut, I instead contend that both ‘C’ strands are themselves riddled with unacknowledged traces of Eurocentric ontologies and epistemologies, albeit to different degrees. For the sake of informed research and teaching, it is necessary to reveal, unravel and overcome such foundational limitations. The review article is structured as follows. I begin with a summary of each volume to highlight what the contributors respectively regard as ‘critical’ and ‘cultural’ analyses of the global political economy. Next, I employ the analogy of the parliamentary polity to assess the engagements of critical and cultural IPE with orthodox IPE. In a related step, I discuss how Eurocentrism afflicts even these decidedly non-orthodox strands and why their limitations matter to the wider discipline. I conclude with a call for mapping further the territory where critical and cultural IPE meet.

New Semiotics: Canada's New Initiatives

Abstract Canada’s relationship to semiotics has been one of engagement, isolation, continued interest, and convergence. Semiotics in Canada has existed for a considerable period of time and, recently, has made itself a niche in the academic landscape by focusing on applications in three specific fields-forensics, robotics, and mathematics. Through our survey of the evolution of semiotics in adjacent and parallel fields, we demonstrate how semiotics serves as a veritable bridge between the sciences and the humanities. Providing a historical, contextual, and heuristic mapping of semiotics as it is currently used in Canadian institutions provides new inroads and applications that are required for the continued success of semiotics.

A Lattice-Based Approach to Percolation in Penetrable Sphere Systems

An heuristic mapping is presented that enables analysis of continuum percolation by penetrable spheres in terms of an analogous lattice model. The resulting framework is based upon the well-known Bethe lattice, which is modified by the inclusion of an adjustable proportion of fully connected subgraphs that provide a particularly simple, albeit operational, vehicle for modeling the effect of inter-particle clustering. The volume fraction at the percolation threshold is calculated as a function of (i) the degree of interpenetrability amongst the spheres, and: (ii) the extent of particle clustering, and the results are compared with findings from Monte Carlo (MC) simulations of this problem. It is found that a suitably chosen ansatz that reflects a monotonic increase in the degree of clustering with increasing inter-sphere penetrability leads to close agreement between percolation thresholds calculated using the present approach and the results of MC simulations.

Integrating profile-driven parallelism detection and machine-learning-based mapping

Compiler-based auto-parallelization is a much-studied area but has yet to find widespread application. This is largely due to the poor identification and exploitation of application parallelism, resulting in disappointing performance far below that which a skilled expert programmer could achieve. We have identified two weaknesses in traditional parallelizing compilers and propose a novel, integrated approach resulting in significant performance improvements of the generated parallel code. Using profile-driven parallelism detection, we overcome the limitations of static analysis, enabling the identification of more application parallelism, and only rely on the user for final approval. We then replace the traditional target-specific and inflexible mapping heuristics with a machine-learning-based prediction mechanism, resulting in better mapping decisions while automating adaptation to different target architectures. We have evaluated our parallelization strategy on the NAS and SPEC CPU2000 benchmarks and two different multicore platforms (dual quad-core Intel Xeon SMP and dual-socket QS20 Cell blade). We demonstrate that our approach not only yields significant improvements when compared with state-of-the-art parallelizing compilers but also comes close to and sometimes exceeds the performance of manually parallelized codes. On average, our methodology achieves 96% of the performance of the hand-tuned OpenMP NAS and SPEC parallel benchmarks on the Intel Xeon platform and gains a significant speedup for the IBM Cell platform, demonstrating the potential of profile-guided and machine-learning- based parallelization for complex multicore platforms.

Resource allocation with multi-factor node ranking in data center networks

In data center networks, resource allocation refers to mapping a large number of workloads to substrate networks. Existing heuristic mapping algorithms evaluate the resources of the nodes according to one resource factor or a product of resource factors, which will probably lead to an imbalance of the resource allocation. Furthermore, neglecting the hops of the substrate paths in the resource allocation may result in low resource utilization. In this paper, we adopt a top-k dominating model to rank the nodes, aiming at balancing these factors to improve resource allocation. Moreover, we propose a novel mapping algorithm TK-Match, which consists of a node mapping stage and link mapping stage. In the node mapping stage, TK-Match maps the virtual nodes to the substrate nodes in terms of the node ranking and the hops of the substrate paths. In the link mapping stage, TK-Match adopts the k-shortest path algorithm to map the virtual links. Extensive simulation experiments show that TK-Match can greatly increase the long-term average revenue and the acceptance ratio.

Heuristic expansion of feature mappings in evolving program families

SUMMARYEstablishing explicit mappings between features and their implementation elements in code is one of the critical factors to maintain and evolve software systems successfully. This is especially important when developers have to evolve program families, which have evolved from one single core system to similar but different systems to accommodate various requirements from customers. Many techniques and tools have emerged to assist developers in the feature mapping activity. However, existing techniques and tools for feature mapping are limited as they operate on a single program version individually. Additionally, existing approaches are limited to recover features on demand, that is, developers have to run the tools for each family member version individually. In this paper, we propose a cohesive suite of five mapping heuristics addressing those two limitations. These heuristics explore the evolution history of the family members in order to expand feature mappings in evolving program families. The expansion refers to the action of automatically generating the feature mappings for each family member version by systematically considering its previous change history. The mapping expansion starts from seed mappings and continually tracks the features of the program family, thus eliminating the need of on demand algorithms. Additionally, we present the MapHist tool that provides support to the application of the proposed heuristics. We evaluate the accuracy of our heuristics through two evolving program families from our industrial partners. Copyright © 2013 John Wiley & Sons, Ltd.

A novel energy-aware multi-task dynamic mapping heuristic of NoC-based MPSoCs

Task mapping is an important issue in network-on-chip (NoC)-based multiprocessor systems-on-chips (MPSoCs) design. The dynamic characteristic of application execution enforces the use of dynamic task mapping. In this article, a hybrid energy-aware dynamic mapping strategy is proposed. The strategy consists of an off-line part and an on-line part. In the off-line part, optimisation tools are used to extract information that helps to reduce the energy consumption in the on-line mapping, while the on-line mapping heuristic makes use of the information. Experimental result shows that the energy consumption is reduced by 21%, on average, compared to the best neighbour heuristic.

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

Virtual network mapping algorithm in the cloud infrastructure

Network virtualization has received considerable attention recently because a Cloud Provider (CP) that is responsible for deploying a substrate network in the cloud infrastructure uses network virtualization to support multiple Virtual Network (VN) requests over the shared substrate network. However, mapping multiple VN requests with constraints on virtual nodes and virtual links into a shared substrate network presents a significant challenge, and is considered an NP-hard problem. In this paper, we propose a heuristic mapping algorithm that handles online VN requests. The node mapping algorithm selects a substrate node for mapping that satisfies both a virtual node's resource requirement and its amount of requested bandwidth. The link mapping algorithm either maps a virtual link to the shortest substrate path that satisfies the requested bandwidth of the virtual link or uses the cut-shortest path approach to map a virtual link to multiple substrate paths that satisfy the requested bandwidth of the virtual link. The path migration algorithm migrates virtual links to different substrate paths to maximize the number of accepted VN requests in a substrate network. Simulation results show that the proposed heuristic mapping algorithm uses resources more efficiently, produces more revenue, and has better performance than existing mapping approaches.

MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs

Processor Systems on Chip (MPSoCs) in order to cope with the increasing applications demands and the tight energy budget of portable devices. The complexity of these systems makes them difficult to program, which has caused academia and industry to look for alternative methodologies and models. In the particular case of multimedia and baseband processing, dataflow models are being proposed and appear to be a sensible choice to represent applications. While high-level models, like dataflow, increase programmers' productivity, new, powerful tools are badly required that lower the abstract specification into an efficient implementation. In this paper, a framework is presented that provides support for mapping multiple dataflow applications onto heterogeneous MPSoCs. The framework is aware of design constraints, provides different means for performance estimation and supports a variety of mapping heuristics. The tool is showcased on three applications on a virtual platform containing heterogeneous processing elements. The heuristics for single applications reported a speedup of up to 40% when compared against random walk. The multi-application component helped to find an appropriate scheduling configuration that met real-time constraints when the three applications were running simultaneously.