Semiconductor Device Fabrication Research Articles

304 半導体生産における特急ロットに対する再ロット割付手法の一提案(OS2 : 生産・物流システムのモデリングとシミュレーション(1))

304 半導体生産における特急ロットに対する再ロット割付手法の一提案(OS2 : 生産・物流システムのモデリングとシミュレーション(1))

Preface to the Focus Issue on Semiconductor Surface Cleaning and Conditioning

The wafer cleaning operations employed in semiconductor device manufacturing do not serve the purpose of building device features by adding films, defining geometries, altering conductivity of semiconductors, or forming contacts and interconnects. Yet, in spite of all this, surface cleaning and conditioning steps are the most frequently applied operations in a typical semiconductor device manufacturing sequence and as such play a critical role in determining manufacturing yield. It is therefore not surprising that the technical papers on broadly understood semiconductor surface processing techniques are common in technical literature, with the ECS publications being no exception. The ECS Journal of Solid State Science and Technology (JSS) Focus Issue on Semiconductor Surface Cleaning and Conditioning is a natural consequence of the Society’s 25 years of involvement with the technical domain of semiconductor surface processing. The series of ECS-sponsored international symposia on semiconductor cleaning technology was initiated in 1989, and was the very first symposium devoted solely to this critically important element of advanced semiconductor manufacturing. Since then, it has been organized biannually during the ECS Fall meetings, with the latest symposium held in San Francisco in October 2013. Overall, over 750 papers delineating the evolution of semiconductor cleaning technology were published in the thirteen proceedings volumes from this symposium series. This is in addition to a number of groundbreaking papers on semiconductor cleaning published in the ECS journals over the years.

Reliability Assessment of the Temperature Profiles Effect on the Power Module

Power devices nowadays possess low switching and conduction loss characteristics owing to the improvement in semiconductor device manufacturing. Insulated gate bipolar transistors are widely utilized in power modules because of such characteristics. When a power module is subjected to cyclic temperature load, the thermal stress resulting from the mismatch among the coefficients of thermal expansion of materials causes fatigue to the interface of the materials. Different operating requirements cause the module to have different temperature profiles. Different dwell times and ramp rates produce different stress relaxation, which eventually affect the reliability of the power module. A 2D finite element model has been established based on an actual sample. The model was subjected to thermal cycling between -40̊C and 125̊C to determine the effect of dwell time and ramp rate on the creep behavior of the solder. The results indicate that dwell time produces accumulative creep strain because of stress relaxation. Furthermore, dwell time at a high temperature leads to evident stress relaxation. Ramp section produces more accumulative creep strain than dwell phase in one thermal cycle. Decreasing the ramp rate increases creep strain and diminishes reliability.

Acid diffusion length in contact hole imaging of chemically amplified extreme ultraviolet resists

Contact holes and line-and-space patterns are the most basic elements in the fabrication of semiconductor devices. In this study, the chemical processes in contact hole imaging were investigated to clarify the optimum acid diffusion length in terms of the quality of latent images. The chemical processes were simulated using a Monte Carlo method based on the reaction mechanisms of chemically amplified extreme ultraviolet (EUV) resists. The theoretical dependence of the optimum acid diffusion length on the exposure dose and half-pitch (diameter) was clarified. At an exposure dose of 20 mJ cm−2, the optimum acid diffusion length (three-dimensional) was 10.7 nm for 28 nm contact holes (56 nm pitch). By decreasing the diameter to 16 nm (32 nm pitch), the optimum acid diffusion length (three-dimensional) was decreased to 8.9 nm, which was smaller than that of line-and-space patterns by 12%. The chemical reactions for the dissolution of resist polymers should be sufficiently induced within these acid diffusion lengths for contact hole imaging.

Multiplex electrical detection of avian influenza and human immunodeficiency virus with an underlap-embedded silicon nanowire field-effect transistor

The label-free electrical detection of the binding of antibodies and antigens of avian influenza (AI) and human immunodeficiency (HIV) viruses is demonstrated through an underlap-embedded silicon (Si) nanowire field-effect transistor. The proposed sensor was fabricated on a silicon bulk wafer by a top-down process. Specifically, a Si nanowire was fabricated by a combined isotropic and anisotropic patterning technique, which is one route plasma etching process. The sensor was fabricated by a self-aligned process to the gate with tilted implantation, and it allows precise control of the underlap region. This was problematic in earlier underlap field-effect transistors fabricated by a conventional gate-last process. As a sensing metric to detect the binding of a targeted antibody, the transfer characteristic change was traced. Before and after differences between the antibody binding results were caused by changes in the channel potential on the underlap region due to the charge effect arising from the biomolecules; this is also supported by a simulation. Furthermore, the multiplex detection of AI and HIV is demonstrated, showing distinctive selectivity in each case. Thus, the proposed device has inherent benefits for the label-free, electrical, and multiplex detection of biomolecules. Moreover, its processes are compatible with commercialized technology presently used to fabricate semiconductor devices. This advantage is attractive for those involved in the construction of a point-of-care testing (POCT) system on a chip involving simple, low-cost and low-risk fabrication processes of novel structures and materials.

A transition solvent strategy to print polymer:fullerene films using halogen-free solvents for solar cell applications

Inkjet printing is a mask-less non-contact deposition technique that is potentially suited for prototyping and manufacturing of thin-film polymer organic semiconductor devices from digital images. However new strategies are needed to achieve films with good macromorphology (i.e., high-fidelity footprint and uniform cross-section) and nanomorphology on unstructured substrates using a conventional ink-jet. Here we report a new transition solvent strategy to provide the desired film macromorphology and ultrafine nanomorphology in regioregular poly(3-hexylthiophene):phenyl-C61-butyric acid methyl ester (P3HT:PCBM) model films, without using chlorinated solvents. This strategy employs a good volatile solvent in combination with a miscible poor solvent that is much less volatile, which is the reverse of the usual low−high boiling-point solvent method. The good solvent suppresses premature aggregation in the ink head. Its removal by evaporation on the substrate leaves the poor solvent that triggers early π-stacking ordering and/or gelation of the polymer matrix that immobilizes the printed fluid on the substrate, suppressing both contact-line depinning and evaporation-induced solvent flow effects. The resultant donor–acceptor nanomorphology is further improved by vacuum drying at an optimal rate that avoids bubble formation. We have systematically characterized P3HT:PCBM films deposited with different solvents and platen temperatures to identify key macro- and nano-morphology determining processes. High-performance printed P3HT:PCBM solar cells were realized. These findings are applicable also to other printing and coating techniques based on low-viscosity inks.

Combining surface X-ray scattering and ellipsometry for non-destructive characterization of ion beam-induced GaSb surface nanostructures

Producing surfaces textured with a homogeneous pattern of nanoscale structures is increasingly important for fabrication of semiconductor devices. Although techniques exist for imaging surface nanostructures on a local scale, these techniques are often impractical for use over large areas for finding average structural information. The nanostructured surface in this study consists of densely packed cones produced by sputtering a mono-crystalline GaSb substrate with a low-energy unfocused ion beam, yielding self-organized cones that are slightly tilted away from the sample normal. Here, we devise an all-optical non-destructive characterization scheme using Grazing-Incidence Small-Angle X-ray Scattering (GISAXS) and Spectroscopic Mueller Matrix Ellipsometry (MME) for obtaining all main dimensions including average height, lateral spacing and packing motifs, and the cone top and bottom diameters. It is further shown that both MME and GISAXS are sensitive to small tilts of the nanocone axis from the surface normal.

Influence of point defects on the structural and electronic properties of SiC nanotubes

AbstractWe have performed studies of the structural and electronic properties of functionalized single wall silicon carbide nanotubes (SW-SiCNTs) with chirality (5,5). Our first principles studies are done using density functional theory. The exchange-correlation energies are modeled according to the Hamprecht-Cohen-Tozer-Handy functional in the generalized gradient approximation (HCTH-GGA) and the DNP basis function with double polarization is applied. To determine the most stable geometry, we have applied the minimum energy criterion considering several initial configurations of the hydroxyl (OH) functional group interacting with the single wall SiCNT. In particular, we tested different orientations of the OH adsorbed on the nanotube surface (oriented towards the Si or C atoms) and at the end of the nanotube. Results indicate that the most favorable geometry corresponds to OH adsorption (chemisorption) at the end of the nanotube. The polarity increases yielding better conditions for solubility and dispersion. The work function of the SW-SiCNT-OH is reduced, which in turn favors conditions for field emission properties (FEPs). Finally, the presence of silicon or carbon mono-vacancies in the functionalized nanotubes suggests this may be a good structure to fabricate semiconductor devices

Determining local residual stresses from high resolution wafer geometry measurements

Multiple thin film deposition steps are central to most semiconductor device fabrication processes. The residual stresses in these thin films can induce both in-plane and out-of-plane distortions to the wafer. These residual stresses can vary spatially across the wafer, and the residual stress distributions can change between lithography steps. This can result in noncorrectable overlay errors in the lithography processes. In order to develop strategies for minimizing overlay errors due to residual stress-induced distortion, there is a critical need for techniques that allow the distributions of residual stresses in deposited thin films to be characterized with high spatial resolution. In this paper, the application of established analytical methods for extracting local residual stress from wafer geometry measurements (shape) is investigated. Three-dimensional finite-element models were used to generate simulated wafer shapes resulting from nonuniform residual stress distributions in thin-films. The results of these finite element simulations were used to assess the effectiveness of established analytical techniques. Furthermore, the results demonstrated that local mean curvature of the wafer shape is a simple metric that can be used to qualitatively describe local residual stress variation across the wafer. The simulations also demonstrated that when residual stresses varied over scales of tens of millimeters that high spatial resolution (<1 mm) shape measurements were required in order to accurately predict local residual stress.

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b -PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5 nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Characterization of the small molecule based organic thin film fabricated by electrospray deposition technique

A novel route for the fabrication of the SM based 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline (BCP) organic thin film by electrospray deposition (ESD) technique has been presented in this paper. The tailoring of the film thickness was also performed by varying the number of deposition passes at a constant substrate speed. The structural and optical characterizations of the fabricated BCP thin film were thoroughly investigated. The energy gap of the fabricated thin film was measured to be 3.5 eV. Furthermore, the electrical performance of the BCP thin film was verified by performing current–voltage measurement of the prototype organic diode device having fabricated BCP film as a buffer layer. The current density–voltage characteristic curve of the organic device showed non linear diode like behavior, thereby confirming the proper interference established between organic diode adjacent layers. At low voltage, the device showed ohmic conduction, where as the space charged limited current and trap charge limited current mechanism have been found to be dominant in the fabricated organic device at higher voltage. Overall, the results suggest that the ESD approach will be promising for organic semiconductor device fabrication at low cost and with low material loss.

Horizontal Capacity Coordination for Risk Management and Flexibility: Pay Ex Ante or Commit a Fraction of Ex Post Demand?

Motivated by the dual-sourcing and contracting practices in the semiconductor industry, we study two prevailing types of contracts that deal with horizontal-capacity-coordination issues between two possible sources: an integrated device manufacturer (IDM) and a foundry. IDMs both design and manufacture semiconductor devices, whereas foundries concentrate only on manufacturing. Because production capacity is capital intensive, IDMs often make decisions on whether to manufacture each device internally or subcontract to foundries. Two types of contracts are most frequently used in such settings. Under α-contracts, a fixed fraction α of ex post realized demand is committed to subcontract to the foundry and serves as an incentive for the foundry to build capacity. Under reservation contracts, an ex ante capacity reservation fee is paid to the foundry as an incentive to build capacity. Because of the different nature of incentives under these contracts, it is unclear which type of contract maximizes the IDM's expected profit. Furthermore, IDMs and their customers often prefer dual sourcing to sole sourcing for risk-management purposes. This paper studies the relationship between the two types of contracts, both with and without dual-sourcing constraints and shows the effect of a dual-sourcing preference on contract selection. Our analysis offers supporting rationale for the coexistence of α-contracts and reservation contracts in practice and provides insights on horizontal capacity coordination beyond the semiconductor industry.

Direct Imaging of 3D Atomic-Scale Dopant-Defect Clustering Processes in Ion-Implanted Silicon

The fabrication of nanoscale semiconductor devices for use in future electronics, energy, and health is among others based on the precise placement of dopant atoms into the crystal lattice of semiconductors and their concurrent or subsequent electrical activation. Dopants are built into the lattice by fabrication processes like ion implantation, plasma-based doping, and thermal annealing. Throughout the fabrication processes fundamental phenomena like dopant diffusion, activation, and clustering occur concurrently with damaging and subsequently recovering the crystal lattice. These processes are described by atomic-scale mechanisms of ion-host atom interaction and have an immense impact on the electrical performance of the resulting devices. Insight in their fundamental nature is of utmost importance for optimizing the performance of nanoscale technologies. In this paper, we demonstrate direct three-dimensional imaging of boron clusters and atoms in crystal defects using field ion microscopy. Our approach allows for the first time the complete characterization of the size and crystallographic orientation of boron-decorated crystal defects. This new method opens a path to image a wide variety of dopant-cluster forms and hence to study the formation and dissolution of boron clusters in silicon on the atomic scale.

Profile measurement of concave spherical mirror and a flat mirror using a high-speed nanoprofiler

Ultraprecise aspheric mirrors that offer nanofocusing and high coherence are indispensable for developing third-generation synchrotron radiation and X-ray free-electron laser sources. In industry, the extreme ultraviolet (wavelength: 13.5 nm) lithography used for high-accuracy aspheric mirrors is a promising technology for fabricating semiconductor devices. In addition, ultraprecise mirrors with a radius of curvature of less than 10 mm are needed in many digital video instruments. We developed a new type of nanoprofiler that traces the normal vector of a mirror's surface. The principle of our measuring method is that the normal vector at each point on the surface is determined by making the incident light beam on the mirror surface and the reflected beam at that point coincide, using two sets of two pairs of goniometers and one linear stage. From the acquired normal vectors and their coordinates, the three-dimensional shape is calculated by a reconstruction algorithm. The characteristics of the measuring method are as follows: the profiler uses the straightness of laser light without using a reference surface. Surfaces of any shape can be measured, and there is no limit on the aperture size. We calibrated this nanoprofiler by considering the system error resulting from the assembly error and encoder scale error, and evaluated the performance at the nanometer scale. We suppressed the effect of random errors by maintaining the temperature in a constant-temperature room within ±0.01°C. We measured a concave spherical mirror with a radius of curvature of 400 mm and a flat mirror and compared the results with those obtained using a Fizeau interferometer. The profiles of the mirrors were consistent within the range of system errors.

Chemical Gradient of Contact Hole Latent Image Created in Chemically Amplified Extreme Ultraviolet Resists

A contact hole pattern as well as a line-and-space pattern is a basic element for the fabrication of semiconductor devices. The critical dimension uniformity and edge roughness of contact hole patterns are critical issues for extreme ultraviolet (EUV) lithography. In this study, the quality of the latent images of contact hole patterns was investigated in terms of the chemical gradient using a simulation on the basis of the reaction mechanisms of chemically amplified EUV resists. The latent image formation of contact hole patterns was compared with that of line-and-space patterns. The latent image quality of contact hole patterns was significantly lower than that of line-and-space patterns. To obtain the same latent image quality as line-and-space patterns, the exposure dose should be increased 1.4±0.1 times. Similarly to the line-and-space patterns, the increase of acid generator concentration and effective reaction radius is effective for the enhancement of latent image quality. For the enhancement of latent image quality of contact hole patterns, the enhancement of the effective reaction radius is more effective in a low exposure dose region than a high exposure dose region.

A Mathematical Model for the Design and Fabrication of Polymer Solar Cells by Spray Coating

Spraying of solution-processable materials such as organic molecules, polymers, nanoparticles, and quantum dots is a viable candidate for the coating process and fabrication of thin film solar cells and other similar semiconductor devices. Spray coating, similar to spray painting in the automotive industry, is a fast process and can be scaled up and used for the roll-to-roll fabrication of solar panels. In this paper, attempts are made to understand various steps of the process and develop a simple model as a design tool. The model equations are solved numerically for the spray coating of a P3HT-PCBM active layer in a polymer solar cell using ultrasonic atomization to investigate the effect of process parameters on the thin film characteristics, such as the film thickness and heat consumption needed to vaporize the solvent. It is concluded that when using spray coating with a small thermal budget, large areas with desired submicron- and nanometer-sized thicknesses can be made in a fast process. Cost of thermal energy and materials decreases with an increase in the substrate speed and nozzle-substrate distance.

New methodology for through silicon via array macroinspection

A new methodology for inspection of through silicon via (TSV) process wafers is developed by utilizing an optical diffraction signal from the wafers. The optical system uses telecentric illumination and has a two-dimensional sensor for capturing the diffracted light from TSV arrays. The diffraction signal modulates the intensity of the wafer image. The optical configuration is optimized for TSV array inspection. The diffraction signal is sensitive to via-shape variations, and an area of deviation from a nominal via is analyzed using the signal. Using test wafers with deep via patterns on silicon wafers, the performance is evaluated and the sensitivities for various pattern profile changes are confirmed. This new methodology is available for high-volume manufacturing of future TSV three-dimensional complementary metal oxide semiconductor devices.

Molecular organization in organic semiconductor thin films observed in real time

Post-deposition molecular rearrangement in thin organic films is revealed by in situ real-time photoelectron spectroscopy during organic molecular beam deposition. Agreement between real time spectroscopy and Monte Carlo modeling confirms the role of nearest-neighbor molecular attraction in driving a time-dependent morphology for oriented films of tin phthalocyanine (SnPc) on a range of substrates. The time-dependent molecular self-organization occurs over timescales comparable to the growth rates and is therefore an important factor in the degradation of thin films of organic semiconductors typically considered for the fabrication of multilayer semiconductor devices.

Application of Directed Self-Assembly Lithography to Semiconductor Device Manufacturing Process

Directed self-assembly (DSA) lithography are recently getting in the spotlight as one of the most promising new generation lithography (NGL) candidates, which have a potential to fabricate semiconductor device patterns down to sub-30nm. In this report, latest experimental and simulation results of contact hole shrink process using the DSA are demonstrated.

Physical Cleaning Enhancement Using Advanced Spray with Uniform Droplet Control

In semiconductor device manufacturing, single wafer processors are widely used in not only BEOL process but also in FEOL process for 2X devices to improve the cleaning efficiency and get the higher productivity. Because the scaled down devices require the minimum substrate loss in the cleaning steps, the physical force by a dual fluid spray is still the main position to improve the cleaning efficiency at the moment comparing with chemical effects as the dissolution of contaminants and/or the lift off of particles. Sato, et al., reported that the relationship between particle removal and droplet characteristics linked to the droplet energy densityEdas following equation [. The kinetic energyEkof droplet is calculated from droplet diameterdand velocityv, as shown in Equation 1.