Fabrication Of Transistors Research Articles

Fabrication and Characteristics of a Zinc Oxide Tunnel Effect Transistor with High Current Output

Fabrication and Characteristics of a Zinc Oxide Tunnel Effect Transistor with High Current Output

NH3/N2 plasma treatment on etched AlGaN surface for high-performance p-GaN HEMTs fabrication

In this work, an NH3/N2 plasma surface treatment technique has been developed to replenish the nitrogen vacancy on the etched AlGaN surface during the p-GaN high-electron-mobility transistors (HEMTs) fabrication. The efficacy of the treatment is confirmed through X-ray photoelectron spectroscopy (XPS) surface characterization. To evaluate the impact of the plasma treatment, three sets of samples with varying etching times are prepared. Remarkably, the drain current of the most severely over-etched device can be recovered from 148 to over 300 mA/mm, accompanied by improved current collapse immunity, a threshold voltage of +1.5 V, and an Ion/Ioff ratio of over 1 × 108. By employing this technique, p-GaN HEMTs can now be fabricated in a uniform and consistent manner.

Fabrication of flexible organic field effect transistors with high carrier mobility via sheath gas-assisted direct writing Poly(3-hexylthiophene) solution

Fabrication of flexible organic field effect transistors with high carrier mobility via sheath gas-assisted direct writing Poly(3-hexylthiophene) solution

Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs

This paper proposes and demonstrates single-crystal Germanium (Ge) growth by elevated-laser-liquid-phase-epitaxy (ELLPE) and the fabrication of Ge Fin field-effect transistors (FinFETs) for the monolithic three-dimensional integrated circuits (monolithic 3D ICs). This technique permitted the fabrication of single-crystalline (100) Ge film and FinFETs without random grain boundaries. In comparison with the poly-Ge FinFETs, the ELLPE Ge FinFETs exhibit superior performance and uniformity. Moreover, the ANSYS simulated maximum temperature of bottom circuits during the ELLPE technique does not exceed 400°C, therefore allowing monolithic 3D integration of ICs.

Modeling of Manufacturing of a Field-Effect Transistor to Determine Condi-Tions to Decrease Length of Channel

Modeling of Manufacturing of a Field-Effect Transistor to Determine Condi-Tions to Decrease Length of Channel

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Investigating the Device Performance Variation of a Buried Locally Gated Al/Al2O3 Graphene Field-Effect Transistor Process

In this study, a process is developed for the fabrication of buried top-gated graphene transistors with Al2O3 as a gate dielectric, yielding devices that can be suitable for not only flexible electronics but also laser-induced graphene (LIG)-based technology implementations. A new processing option is presented with the use of tetraethyl-orthosilicate (TEOS) as an etch stop for contact via etching of Al2O3. Buried locally gated Al/Al2O3 graphene field-effect transistors (GFETs) are fabricated with Dirac points as low as 4 V, with a metal-to-graphene contact resistance as low as ∼1.7 kΩ·µm, and an average hole mobility of 457.97 cm2/V·s with a non-uniformity of 93%. Large device variation and non-uniformity in electrical performance are not uncommon for graphene-based devices, as process-induced defects play a major role in such variation. AFM, SEM, Raman spectroscopy, and model fitting indicated that the rough Al/Al2O3 surface was the main factor for the observed device variation. AFM analysis indicated a graphene surface roughness Ra of 16.19 nm on top of the buried Al/Al2O3 gate in contrast to a Ra of 4.06 nm over Al2O3/SiO2. The results presented indicate the need to reduce device variability and non-uniformity by improving transfer methods, as well as the use of smoother surfaces and compatible materials. The presented analyses provide a framework with which other researchers can analyze and correlate device variation and non-uniformities while methods to reduce variability are investigated.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

High-Throughput Mechanical Exfoliation for Low-Cost Production of van der Waals Nanosheets.

A method is presented for scaling up the production of flakes of van der Waals materials via mechanical exfoliation. Using a roll-to-roll setup and an automatized, massive parallel exfoliation process, adhesive tapes with a high density of nanosheets of van der Waals materials are produced. The technique allows for obtaining a good trade-off between large lateral size and excellent area scalability, while also maintaining low cost. The potential of the method is demonstrated through the successful fabrication of field effect transistors and flexible photodetectors in large batches. This low-cost method to produce large area films out of mechanically exfoliated flakes is very general, and it can be applied to a variety of substrates and van der Waals materials and, moreover, it can be used to combine different van der Waals materials on top of each other. Therefore, it is believed that this production method opens an interesting avenue for fabrication of low-cost devices while maintaining a good scalability and performance.

Shellac as dielectric materials in organic field-effect transistors: from silicon to paper substrates

Recent advances in the design and preparation of electroactive materials, particularly semiconducting and conductive polymers, have resulted in the creation of novel organic electronics with advanced functionality and performance competitive with that of devices made of silicon. With an increasing number of organic and printed electronics being engineered and produced at a larger scale, the environmental cost of the final organic electronic devices (life cycle, environmental impact, etc) needs to be considered. While e-waste is already a growing global problem, improving the sustainability of emerging electronics through a careful materials selection is highly desirable. In this work, we explore the use of shellac as a sustainable greener dielectric material in organic field-effect transistors. A careful examination of shellac in combination with diketopyrrolopyrrole-based semiconducting polymers was performed on rigid substrates through atomic force microscopy (AFM) and the fabrication of thin film transistors. All devices made from this green dielectric showed good performance and device characteristics. Building from this investigation, shellac was further integrated with paper substrates to fabricate paper-based thin film transistors. Thin film samples based on shellac on both silicon wafer and paper substrates were characterized by AFM to investigate solid-state morphology of shellac and selected semiconducting materials. Through careful optimization of the device architecture and processing time, device characteristics and performances on paper substrates (average charge mobilities and on/off current ratios) were comparable to those of devices prepared on silicon wafers, confirming that shellac, in combination with organic semiconducting polymers, can be an advantageous dielectric material to be used for the fabrication of greener and sustainable thin film electronics from renewable feedstocks and components.

Fabrication and characterization of field-effect transistors based on MoS2 nanotubes prepared in anodic aluminum oxide templates

Field-effect transistors (FETs) based on MoS2 nanotubes prepared in anodic aluminum oxide (AAO) templates have been fabricated and demonstrated in this work. MoS2 nanotubes were prepared by the thermal decomposition of (NH4)2MoS4 precursors in the AAO template. The diameter of the MoS2 nanotubes was approximately 80 nm, which corresponded to the size of the AAO template. Schottky-type FETs were prepared with Au and Pt electrodes, and the FETs exhibited n-type behavior, with on/off ratios that exceeded 103 at VSD = 0.5 V.

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

Downsizing the Channel Length of Vertical Organic Electrochemical Transistors.

Organic electrochemical transistors (OECTs) are promising building blocks for bioelectronic devices such as sensors and neural interfaces. While the majority of OECTs use simple planar geometry, there is interest in exploring how these devices operate with much shorter channels on the submicron scale. Here, we show a practical route toward the minimization of the channel length of the transistor using traditional photolithography, enabling large-scale utilization. We describe the fabrication of such transistors using two types of conducting polymers. First, commercial solution-processed poly(dioxyethylenethiophene):poly(styrene sulfonate), PEDOT:PSS. Next, we also exploit the short channel length to support easy in situ electropolymerization of poly(dioxyethylenethiophene):tetrabutyl ammonium hexafluorophosphate, PEDOT:PF6. Both variants show different promising features, leading the way in terms of transconductance (gm), with the measured peak gm up to 68 mS for relatively thin (280 nm) channel layers on devices with the channel length of 350 nm and with widths of 50, 100, and 200 μm. This result suggests that the use of electropolymerized semiconductors, which can be easily customized, is viable with vertical geometry, as uniform and thin layers can be created. Spin-coated PEDOT:PSS lags behind with the lower values of gm; however, it excels in terms of the speed of the device and also has a comparably lower off current (300 nA), leading to unusually high on/off ratio, with values up to 8.6 × 104. Our approach to vertical gap devices is simple, scalable, and can be extended to other applications where small electrochemical channels are desired.

ISFET Fabrication and Characterization for Hydrogen Peroxide sensing

This work presents the Ion-Sensitive Field Effect Transistor (ISFET) fabrication and electrical characterization for hydrogen peroxide sensing. Two configurations were set up to evaluate the devices sensitivity to the concentration of the solution. First, measurements with one electrode in the sample solution (contained over the gate area) were performed, but the results may not be directly related to the characteristics of the solution, due to the prevalence of secondary effects. The second method, using two electrodes in the sample solution, shows a higher sensitivity at increasing hydrogen peroxide concentrations, in smallest intervals when compared to measurements with one electrode.

A New Look at Silicon Carbide

Silicon Carbide, SiC is one of the most widely used materials that plays a critical role in industries such as: aerospace, electronics, industrial furnaces and wear-resistant mechanical parts among others. Although SiC is widely used in electronics and other high technology applications, the metallurgical, abrasive, and refractory industries are dominate by volume. It is only in the last five or six years that SiC has gained a new and important role in the semiconductor industry. SiC has become a key material in the drive towards electrification. It’s unique physical properties, wide band gap, especially, high temperature performance and “ease of manufacturability makes it a key material going forward. The physical properties that make SiC so unique also represent some serious problems to large scale manufacturing of SiC diodes, transistors and modules. SiC is a very tough material, it has a Mohs hardness rating of 9.5 approaching that of diamond. Just as the semiconductor industry needed high quality defect free silicon wafers to move forward, so did the SiC industry. High quality defect free wafers have just come into the market. They are 4 and six wafers that will allow SiC. These boules can be “sliced” in wafers and run on a standard CMOS fabrication process. Next comes the dicing of the wafers into devices. A diamond saw has to be run at a very slow rate to a material almost as hard as the diamond itself. Die attach brings an interesting problem the devices are generally rate at 200+ deg C and voltages >1000W. Standard epoxy and even Au/Si eutectic die attach has issues has issues at these extreme operating conditions. Lastly, the epoxy molding compound has to be capable of withstanding the harsh conditions and not breakdown. These are all challenges that are being met today. This is a continuing story of how the semiconductor industry adapts to ever changing requirements

Charge transfer enabled by the p-doping of WSe2 for 2D material-based printable electronics

Here, we report the fabrication of high-performance printable WSe2 transistors via the doping of p-type FeCl3 molecules (hole mobility: ∼1.5 cm2 V−1 s−1; on/off ratio: ∼106). A complementary inverter is demonstrated with p-WSe2 and n-MoS2 transistors, which highlights its potential for application in future two-dimensional material-based printable electronics.

Design and Fabrication of Ultrathin Nanoporous Donor-Acceptor Copolymer-Based Organic Field-Effect Transistors for Enhanced VOC Sensing Performance.

The development of organic field-effect transistor (OFET) chemical sensors with high sensing performance and good air stability has remained a persistent challenge, thereby hindering their practical application. Herein, an OFET sensor based on a donor-acceptor copolymer is shown to provide high responsivity, sensitivity, and selectivity toward polar volatile organic compounds, as well as good air stability. In detail, a polymer blend of N-alkyl-diketopyrrolo-pyrrole-dithienylthieno[3,2-b]thiophene (DPP-DTT) and polystyrene is coated onto an FET substrate via shearing-assisted phase separation (SAPS) combined with selective solvent etching to fabricate the DPP-DTT-based OFET device having an ultrathin nanoporous structure suitable for gas sensing applications. This is achieved via optimization of the film morphology by varying the shear rate to adjust the dynamic balance between the shear and capillary forces to obtain an ultrathin thickness (∼8 nm) and nanopore size (80 nm) that are favorable for the efficient diffusion and interaction of analytes with the active layer. In particular, the sensor presents high responsivities toward methanol (∼70%), acetone (∼51.3%), ethanol (∼39%), and isopropyl alcohol (IPA) (∼29.8%), along with fast response and recovery times of ∼80 and 234 s, respectively. Moreover, the average sensitivity was determined to be 5.75%/ppm from the linear plot of the responsivity against the methanol concentration in the range of 1-100 ppm. Importantly, the device also exhibits excellent long-term (30-day) air and thermal storage stability, thereby demonstrating its high potential for practical applications.

Biosignal Amplifiers Based on Low‐Noise Organic Transistors with Printed Electrodes

AbstractThe monitoring of microvolt‐level biosignals such as electroencephalograms requires the application of low‐noise signal amplifier circuits, which, for single‐use cases, must be fabricated for disposability using low‐cost manufacturing techniques. One promising solution for the production of low‐cost amplifier circuits for digital biosensing is the emerging technology of low‐noise printed circuits. Here, a low‐noise‐electrode printing process for organic transistors that can carry out precision measurement of brain activity using a low‐noise organic amplifier is proposed. In the transistor fabrication process, Ag electrodes are processed via flat stamp parallel printing, and fine‐process optimization to minimize the charge‐trapping effect enables a three‐order reduction in transistor noise. The low‐noise transistors are used to produce an organic pseudo‐complementary metal‐oxide‐semiconductor amplifier with a small noise level of 2.2 µVp‐p at 10 Hz, which enables precision brain wave monitoring in a close correlation with signals obtained using a commercialized measurement system.

Proton-Gated Synaptic Transistors, Based on an Electron-Beam Patterned Nafion Electrolyte.

Neuromorphic processors using artificial neural networks are the center of attention for energy-efficient analog computing. Artificial synapses act as building blocks in such neural networks for parallel information processing and data storage. Herein we describe the fabrication of a proton-gated synaptic transistor using a Nafion electrolyte thin film, which is patterned by electron-beam lithography (EBL). The device has an active channel of indium-zinc-oxide (IZO) between the source and drain electrodes, which shows Ohmic behavior with a conductance level on the order of 100 μS. Under voltage applications to the gate electrode, the channel conductance is changed due to the injection and extraction of protons between the IZO channel and the Nafion electrolyte, emulating various synaptic functions with short-term and long-term plasticity. When positive (negative) gate voltage pulses are consecutively applied, the device exhibits long-term potentiation (depression) at the same number of steps as the number of input pulses. Based on these characteristics, an artificial neural network using this transistor shows ∼84% image recognition accuracy for handwritten digits. The subject transistor also successfully mimics paired-pulse facilitation and depression, Hebbian spike-timing-dependent plasticity, and Pavlovian associative learning followed by extinction activities. Finally, dynamical pattern image memorization is demonstrated in a 5 × 5 array of these synaptic transistors. The results indicate that EBL patternable Nafion electrolytes have great potential for use in the fabrication and circuit-level integration of synaptic devices for neuromorphic computing applications.

Fabrication and characterization of ultra-thin ZnO based bottom gate thin film transistor for UV detection

An RF sputtered ZnO thin film was utilized in a thin film transistor (TFT) fabrication. The film was fabricated on SiO2 gate oxide that was thermally grown on Si Substrate. Few lithography steps were used to fabricate the device and device structure was proved to be a bottom gate TFT. The grown film was ultra thin of 25 nm thickness and the Si wafer was n-type. The structural and optical properties of ZnO films were investigated by Field Emission Scanning Electron Microscopy (FESEM), X-Ray Diffraction (XRD) and Photo luminance (PL) spectroscopy. The photo luminance study confirmed a high-quality absorbance in UV spectra and relatively good transmittance in the visible region. The electrical performance of the transistor was studied using Proxima B1500 and the on/off current ratio was measured to be ∼107. The ZnO bottom gate TFT is simulated using the commercial TCAD tool Silvaco ATLAS™. Later the simulated I–V characteristic of the device is compared with the experimental one and both are in fairly good agreement. Further the UV detection capability of the fabricated device was studied by using UV LED light of 365 nm wavelength. The measured value of threshold voltage was found to be 9V under dark light and 10V under UV light.