In multi-crystalline silicon (mc-Si), the detrimental effect of impurities and grain boundaries (GBs) on charge carrier transport has driven the research focus since many years. In view of curing these limitations, we present an innovative method to enhance the optoelectronic performance of mc-Si wafers via a combination between GBs grooving and porous silicon (PS) gettering. A preferential grooving of GBs was achieved using the HF/HNO3 based solution, the PS layers were formed on both sides of the samples using stain-etching method and the gettering experiment was performed at temperatures ranging from 750 to 900 °C. As a result, it has been shown that the rapid thermal annealing process with chemical grooving gives a positive trend of improvement of the electronic quality and found to be more efficient when used in combination with PS. After removing the PS layer, the minority carrier lifetime increases by a factor of more than 27. In addition, a significant enhancement of majority carrier mobility was obtained, which led to an important decrease of the resistivity.