Macromodel Function Research Articles

Power macromodeling technique and its application to SoC‐based design

AbstractLow power is becoming a more crucial performance metrics in system‐on‐chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation.This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero‐delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP‐based SoC system, the average error is estimated at 11.42%.

Efficient power analysis approach and its application to system-on-chip design

Low-power is becoming more crucial performance metrics in system-on-chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation.This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm (GA) is implemented for the generation of sequences of input signals during the power estimation procedure. The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte-Carlo zero-delay simulation is performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. The meta-modeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In experiments with the IP-based SoC system, the average error is estimated 11.42%.

Power analysis approach and its application to IP-based SoC design

Purpose Low-power consumption has become an important issue that cannot be ignored in System-on-Chip (SoC) design. The key challenge encountered by system design is how to maintain balance between the estimation accuracy and speed. This paper aims at demonstrating an accurate and fast power estimation technique. Design/methodology/approach The methodology adopted in the paper is to use input patterns with the predefined statistical characteristics which helps to analyze the average power consumption of the different intellectual-property (IP) cores and the interconnects/buses in SoC design. Similarly the paper has implemented Genetic algorithm (GA) to generate sequences of input signals during the power estimation procedure. Findings The GA concurrently optimizes the input signal characteristics that influence the final solution of the pattern. In addition to that, a Monte-Carlo zero-delay simulation is also performed for individual IP core and bus at high-level. By the simple addition of these cores/buses, power is predicted by a novel macro-model function. In experiments, the average error is estimated at 13.84%. Research limitations/implications To present the research findings with clarity and to avoid complexities, the paper does not consider delay factors like glitches, jitter etc. in the power model. Practical implications The proposed methodology allowed accurate power/energy analysis of practical applications mapped onto Network-on-Chip (NoC) based Multiprocessors SoC platform. It enables the performance analysis of different design alternatives under the load imposed by complex applications. Originality/value This paper is an original contribution and the results demonstrate that our novel technique could be implemented to achieve fast and accurate power estimation in the early stage of any SoC design.

Power estimation for intellectual property-based digital systems at the architectural level

Estimating power consumption is becoming the critical issue that cannot be neglected in VLSI (very large scale integration) design procedure. Low power solutions are an imperative requirement for the SoC (System-on-Chip) flow that gives designers a powerful methodology to analyze, estimate, and optimize today’s increasing power concerns.We present an efficient power macro-modeling technique at the architectural level for digital electronic systems. This technique estimates the power dissipation of intellectual property (IP) components to their statistical knowledge of the primary inputs/outputs. During the power estimation method, the sequence of an input stream is generated by a genetic algorithm (GA) using input metrics and the macro-model function to construct a set of functions that map the input metrics of a macro-block to its output metrics. Then, a Monte Carlo zero-delay simulation is performed and the power dissipation is predicted by a macro-model function. The most important contribution of the technique is that it allows fast power estimation of IP-based design by the simple addition of individual power consumption. This makes the power modeling of SoCs an easy task that permits evaluation of power features at the architectural level. In order to evaluate our model, we have constructed IP-based digital systems using different IP macro-blocks. In experiments with an individual IP macro-block the average error is 1–2% and for an entire IP-based system with interconnects, the error range is from 9% to 15%. The preliminary results are effective and our macro-model provides accurate power estimation.

Power estimation technique for DSP architectures

The main goal of power estimation is to optimize the power consumption of a electronic design. Power is a strongly pattern dependent function. Input statistics greatly influence on average power. We solve the pattern dependence problem for intellectual property (IP) designs. In this paper, we present a power macro-modeling technique for digital signal processing (DSP) architectures in terms of the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by a genetic algorithm using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macro-model function is built from power dissipation results. From then on, this macro-model function can be used to estimate power dissipation of the system just by using the statistics of the macro-block's primary inputs. In experiments with the DSP system, the average error is 26%.

Automated Energy/Performance Macromodeling of Embedded Software

This paper presents an automatic methodology to perform characterization-based high-level software macromodeling. Macromodeling-based estimation can be used to speed up simulation-based software-performance/energy estimation. High-level software macromodels, which are significantly faster to evaluate than detailed models of the target hardware platform, can be used instead of the latter during simulation, resulting in orders-of-magnitude simulation speedup. However, in order to realize this potential, significant challenges need to be overcome in both the generation and use of macromodels-including how to identify the parameters to be used in the macromodel, how to define the template function to which the macromodel is fitted, etc. The authors' methodology attempts to address the aforementioned issues. Given a subprogram to be macromodeled for execution time and/or energy consumption, the proposed methodology automates the steps of parameter identification, data collection through detailed simulation, macromodel template selection, and fitting. The authors propose a novel technique to identify potential macromodel parameters and perform data collection, which draws from the concept of data-structure serialization used in distributed programming. They utilize symbolic-regression techniques to concurrently filter out irrelevant macromodel parameters, construct a macromodel function, and derive the optimal coefficient values to minimize fitting error. Experiments with several realistic benchmarks suggest that the proposed methodology improves estimation accuracy and enables wide applicability of macromodeling to complex embedded software, while realizing its potential for estimation speedup