Power macromodeling technique and its application to SoC‐based design

Abstract

AbstractLow power is becoming a more crucial performance metrics in system‐on‐chip (SoC) design. Power function is largely determined by input patterns. The characteristics of these patterns have a major influence on power dissipation.This paper demonstrates power estimation technique using input patterns with the predefined statistical characteristics that helps to analyze the average power consumption of the different intellectual property (IP) cores and the interconnects/buses in SoC design. Genetic algorithm is implemented for the generation of sequences of input signals during the power estimation procedure. The genetic algorithm concurrently optimizes the input signal characteristics that influence the final solution of the pattern. Then, a Monte Carlo zero‐delay simulation is performed for individual IP core and bus at a high level. By the simple addition of these cores/buses, power is predicted by a novel macromodel function. The metamodeling technique is adopted to improve accuracy of the samples of realistic data for the quality of results. In the experiments with the IP‐based SoC system, the average error is estimated at 11.42%.