Macrocell Generator Research Articles

A source sensing technique applied to SRAM cells

A new CMOS cell design is proposed, analyzed, and implemented in an ASIC macrocell generator to evaluate the performance and reliability of sensing the ground return current produced in the cell during read access. Both single and dual port cell configurations are studied for static noise margin (SNM), writing requirements, and source offset voltage effects. To frame the advantages and differences of the SSS cell, a comparison is made to several conventional SRAM cells. Noise margins are found to be the same or better than conventional cells, and where design allows cell device ratio optimizations, single ended access cells can generate greater SNM than differential cells. The source sensing technique was evaluated by inserting the new cell in a 0.5 /spl mu/m ASIC memory block and tested on standard ASIC test sets. >

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port

A silicon compilable macrocell implementing the IEEE S1149.1 Test Port has been developed and implemented to facilitate the use of the 1149.1 standard in application-specific integrated circuits (ASICs). The macrocell is intended as a drop-in block which supports the basic boundary-scan functions. Options are provided to support different possible user configurations (as supported by the 1149.1 standard) by merely recompiling the macrocell generator with a different set of user parameters.

Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction

A method to design cell libraries for macrocell layouts, which are constructed as an array of cells, is discussed. It is based on symbolic layout and a hierarchical compaction algorithm. This algorithm provides automatic terminal fitting and compacts cells in such a way that translated and mirrored cells are kept identical. The cells can be changed with a set of parameters by a macrocell generator. The compaction technique then guarantees that no design-rule errors occur for any combination of the parameter values. The method also allows easy adaptability to circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established its cells can be used over and over again with different personality matrices for fast generation of correct layout.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

ALGIC—a silicon compiler system for digital signal processing

This paper describes the ALGIC silicon compiler system for digital signal processing applications. Starting from a structural and functional description of a digital VLSI circuit, ALGIC generates automatically the corresponding layout in a full-custom design style. The main components of ALGIC are a system monitor module, a parametrisable macro-cell generator, an appropriate floorplanner giving a 100% routing solution and a block-oriented timing verifier. An essential feature of the system is the high degree of integration between all the program modules achieved using the concept of abstract data types.