Macromodel Simulation Research Articles

Two New Voltage-Mode Sinusoidal Quadrature Oscillators Employing Second-Generation Voltage Conveyors

This article presents an application of a second-generation voltage conveyor (VCII) as a quadrature oscillator. The controlling parameters of the presented circuits, i.e. oscillation condition and oscillation frequency are tuneable without affecting the other. Both the single-resistance-controlled oscillators employ only two VCII, two grounded capacitors, and three grounded/ virtually grounded resistors. To strengthen the design idea regular mathematical analysis such as ideal, non-ideal, parasitic, frequency stability, phase noise analysis, and sensitivity calculations have been performed. To validate the proposed networks, the simulations have been carried out using 180 nm CMOS technology parameters, and experimental studies have also been performed using commercially available integrated circuits.

Research on pipeline connection structure of microwave load water-cooling system for spacecraft thermal test

The microwave load water-cooling system was operated in a vacuum cold black environment, and the pressure difference between the inside and outside of the water pipe could reach 0.3 to 0.4 MPa. To ensure the tightness of the water pipe, a conical seal structure was selected, the macro-static model and micro-boundary element contact model were established for the two forms with and without the Viton seal. The macro model simulation was performed by the finite element method to obtain the stress distribution inside the conical structure under different preload stress, the relationship between the contact pressure of the conical sealing interface and the contact area of the O-ring sealing interface as a function of preload stress; the method was used to calculate the micro-contact model, and the critical contact pressure and contact area to achieve the sealing requirements were obtained respectively without Viton seal and with Viton seal. As a result, a conical seal structure with a Viton seal was finally chosen for application. After verification, the structure meets the requirements for the use of microwave load water-cooling systems during the vacuum thermal test.

Monetary Policy Regimes in Small Open Economies: The Case of Sri Lanka*

This paper quantifies the performance of five alternative monetary policy regimes in controlling macro volatility in a small open, emerging economy. The effects of supply, demand and external shocks are analyzed using a generic structural macro model and Monte Carlo simulation, calibrated to the case of Sri Lanka. Investigated regimes separately target the exchange rate, monetary aggregates, nominal GDP, the consumer price index inflation rate and a Taylor composite of output gaps and inflation. The results suggest that nominal GDP targeting minimizes real GDP volatility, and when stabilizing economic welfare is the objective, volatility is minimized under inflation targeting and Taylor policy rules. The IT regime is most effective under demand and external shocks, which have grown more prominent as product and financial markets have opened.

Macro modeling of steel-concrete composite shear walls

To date, many researchers have developed various types of macro models to simulate the general response of conventional steel plate and reinforced concrete shear walls. Although extensive numerical and experimental studies have been conducted to assess the seismic response of steel-plate concrete composite shear walls, a robust macro-model for simulation of the cyclic response of such systems has not been developed yet.Herein, a fiber-based model is proposed to simulate the nonlinear seismic response of SC walls using PERFORM-3D program. The details of the proposed model, including material properties, element type, and boundary condition, are presented. The proposed model is validated using the available test data of seventeen SC wall specimens with and without boundary elements. Based on the analysis results, this novel approach can capture the global response of SC shear walls including initial stiffness, peak shear strength and its corresponding displacement, stiffness and strength degradation, and pinching behavior accurately. The proposed macro model for SC shear walls can be considered as a reliable tool to extend the engineering application of SC walls in the building industry.

Performance analysis and macromodel simulation of steel frame structures with beam-column joints using cast steel stiffeners for progressive collapse prevention

Progressive collapse is an important failure mechanism that must be considered in the design of critical and essential buildings. For steel moment structures, beam-column joints, which act as transportation hubs of forces, are crucial members to resist progressive collapse. This research investigated the effectiveness of beam-column joints with cast steel stiffeners (CSS) in steel moment frames for progressive collapse resistance. A computationally efficient macromodel that can be used for routine design of steel moment frame buildings with CSS was developed in this paper. The developed model, which considers the deformation of joints with CSS and the catenary action effects during progressive collapse, was validated using a 3D solid finite-element model. Subsequently, the macromodel was utilized to calculate the proper dynamic increase factor for steel moment frame structures with beam-column joints using CSS. The results show that the frame with CSS is less vulnerable to gravity-induced progressive collapse than frames with welded beam-column joints without stiffeners. The proposed macromodel is effective and a dynamic increase factor of 1.6 is suitable for dynamic progressive collapse analysis of steel moment frame structures using beam-column joints with CSS.

Electronically Tunable Dual-Input Integrator: Synthetic Immittance Function Realizability

ABSTRACTA new electronically tunable differential input integrator (ETDII) using the composite current feedback amplifier (CFA) and multiplication-mode current conveyor (MMCC) building block is presented, wherein the control voltage (Vc) of the MMCC tunes its time constant (τ). Effects of the device parasitic capacitances had been examined and appropriate compensation design is proposed to obtain high-quality (q) realization. Analysis shows that τ is practically active insensitive to device port mismatch errors (ϵ). A quadrature voltage controlled oscillator (VCO) is implemented utilizing the ETDII after suitably configuring a double-integrator loop with grounded capacitors in the same topology. With the loop closed, the ETDII topology realizes some new electronically tunable synthetic immittance function at appropriate nodes. Satisfactory experimental results for the proposed realizations had been verified with PSPICE macro-model simulation and by hardware test.

Multioutput LED Drivers With Precise Passive Current Balancing

According to the detailed essential concept of current balancing presented in this paper, an improved passive current balancing method based on capacitive scheme is proposed consequently. This method can also be extended to the application of isolated multioutput LED drivers. Compared with active method to achieve current balancing among the multioutput LED strings, the passive method exhibits its attractive advantages in cost efficiency and balancing accuracy. Both the macromodel simulation and the prototype experiment results demonstrate the feasibility of the proposed method. The proposed method can achieve precise balancing in steady state and dynamic state even with considerably different peripheral parameters.

Modelling methodology and experimental verification of the permanent-magnet-biased saturation-based fault current limiter

Regarding the line-type permanent-magnet-biased saturation-based fault current limiter (PMFCL), flux leakage effect is introduced in the modelling scheme to justify and ameliorate the theoretical analysis. The research indicates that the current flowing through the external circuit and the flux through the saturated iron-core are two principal variables in combining the external circuit with the magnetic topology of a PMFCL. Equivalent models coupling both the electric and magnetic circuits are established, in which the PMFCL is considered as a controlled voltage source dominated by the flux through the iron-core. A macro-model for simulation is achieved with MATLAB/SIMULINK software and the wrap-to-zero module is presented to substitute the switch in the simulation model. Experiments are further conducted and are thereby compared with the simulation results, which have verified the effectiveness and the accuracy of the proposed modelling methodology.

New Integrators and Differentiators Using a MMCC

Using the new building block Multiplication-Mode Current Conveyor (MMCC), some inverting/non-inverting type integrator and differentiator designs are presented, wherein the time constant (τ) is tuned electronically. The MMCC is implemented by a readily available chip-level configuration using a multiplier (ICL 8013) and a current feedback amplifier (AD-844 IC) CFA. Detailed analysis, taking into account the device non-idealities, had been carried out that indicates slight deviations affecting the values of the nominal time constant but the design is practically insensitive to the port mismatch errors (e). Satisfactory response on wave conversion, for signal frequencies up to 600 Khz had been verified with both hardware circuit test and PSPICE macromodel simulation.

Analysis the Interface of Amplifier in GPON System by PSpice

Model help to understand the system there may be a signal reflection and impedance matching problem. Most fiber integrated circuits from Maxim use Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS) I/O formats. Language can be set up through the PSpice circuit model of the IC, with an ideal voltage controlled current source of alternative sources and active circuit elements. And the use of spice macro-model simulation to test the circuit performance of the chip interface design. In this paper, it takes the model of amplifier IC in GPON receiver front-end for example to shows the steps and importance of interface simulation in GPON system by PSpice macro-model.

Estonia’s potential growth revisited

There have been several data revisions to output statistics in Estonia during the past six years as methodologies have been harmonised. These changes are significant enough to require corrections to the earlier understanding of Estonia’s potential economic growth rate. In this paper the latest data vintage from 2009 is used to estimate Estonia’s potential output growth and output gap. The production function approach that has been used shows that the gap varies quite extensively, ranging from –8% in 1999 to +8% in 2007, while the average potential growth rate in 1997–2009 was around 6%. The macro model simulations expect the potential growth rate to fall in the future. The fall in the marginal productivity of production inputs makes growth slow to about 4–5% in the next five years, if there are no additional shocks to the economy.

ON THE NEW DESIGN OF SINUSOID VOLTAGE CONTROLLED OSCILLATORS USING MULTIPLIER IN CFA-BASED DOUBLE INTEGRATOR LOOP

The design and analysis of some new voltage controlled oscillators with sinewave output are proposed. The configurations are based on the implementation of double-integrator loop (DIL) using the Current Feedback Amplifier (CFA) device. For voltage control of the time constants of the DIL, the ICL-8013 multiplier element has been appropriately utilized in a feedforward/feedback connection within the loop. The oscillation frequency (ωo) is tunable by the d.c. control voltage (Vc) of the multiplier. The active ωo-sensitivity relative to the CFA port errors (ε) is quite low. The VCO practical performance had been tested both with hardware implementation and with PSPICE macromodel simulation, in a typical frequency range of 50 KHz–1.5 MHz.

A New SPICE Macro-Model for Simulation of Single Electron Circuits

In this paper we have proposed a new and more accurate macro-model for simulation of single electron transistors (SETs). Furthermore, this model includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition to achievement of more accuracy, we have added a switched capacitor circuit, as a quantizer, to evaluate the time of electron tunneling through the barrier. We used HSPICE for high-speed simulation and observed that our macro-model gives more accurate results than of the other models when compare with SIMON 2.0. This model is completely applicable for calculating the delay time of complicated circuits.

Active-R tunable integrators using a current differencing buffered amplifier

Some new active-R integrator realisation schemes using the transadmittance pole of a current differencing buffered amplifier (CDBA) element are presented. The time constant (τ) is tunable by a single resistor whereas the integrator quality factor (Q) can be made very large with suitable realisability design. The active sensitivities of τ and Q are extremely low. As an application, a variable frequency sinusoid oscillator utilising the integrators in a loop has also been designed. Practical results using the hardware implementation and by PSPICE macromodel simulation are included for a frequency range of 1 MHz < f < 24 MHz.

Single CFA-Based Integrator, Differentiator, Filter, and Sinusoid Oscillator

A new multifunction configuration using a single current feedback amplifier (CFA) and a few RC components is presented. The analysis for the various signal processing function realizability had been carried out by utilizing the internal parasitic and transimpedance elements of the CFA (AD-844 or 846) device. The circuit implements the functions of integrator/differentiator, high-selectivity (Q ges 20) filters, and sinusoid oscillator (Q rarr infin) on the same topology with the appropriate design. Adjustment of the time constant (T), filter quality (Q), and oscillation frequency (omegao) may be obtained with single-component variation at extended frequency ranges (1-30 MHz). All of the proposed functional performances had satisfactorily been verified with PSPICE macromodel simulation and by hardware circuit implementation.

Selective Filters and Sinusoidal Oscillators Using CFA Transimpedance Pole

Using a single current feedback amplifier (CFA) device, two new variable frequency sinusoidal RC oscillators are presented. The transadmittance pole of the device (AD-844) has been utilized in the design for generating sine wave signals covering a range of 1 MHz≤f 0≤31 MHz. Under open-loop conditions, both circuits exhibit resonance characteristics at moderate Q-values (1≤Q≤9). These responses have been experimentally verified with hardware circuit implementation and PSPICE macromodel simulation.

Analysis of Pt Catalyst Degradation of a PEFC Cathode by TEM Observation and Macro Model Simulation

Pt particle size distributions at various positions in a cathode catalyst layer were evaluated by transmission electron microscopy (TEM) observation before and after a potential cycling test and by simple 1D macro model simulation to describe the degradation phenomena. Both the results showed similar tendencies: at the position near the membrane, the number of Pt particles for all sizes decreased with time; in contrast, at the position near the gas diffusion layer (GDL), the number of large Pt particles increased. The validity of this model is not verified yet because the precision of parameters is not confirmed. This model, however, can be used as a tool for deeper understanding of Pt degradation.

Third order lowpass Butterworth filter function realisation using CFA

A new realisation scheme for third order lowpass Butterworth filter function (BFF) using two CFA devices and few RC components is presented. The design equations utilise the transadmittance elements of the devices. The maximally flat response at select frequencies in the range 5 MHz ≤ f o ≤ 30 MHz had been verified with PSPICE macromodel simulation and by hardware circuit implementation using the AD-844 device. The active sensitivities are quite low. The simulation result and the measured responses are included for f o = 5.1 MHz and 22.2 MHz.

Tunable active-R oscillator using a CFA

A novel tunable sinusoid oscillator design using a negative polarity current feedback amplifier (CFA) and only three resistors, is presented. The design utilises the transimpedance pole of the CFA device (AD-844). Independent fo-tunability (3MHz to 40MHz) had been verified with both PSPICE macromodel simulation and hardware circuit implementation. The genreration is practically active insensitive.

Fast and reliable top-level simulation strategy for mixed-signal integrated circuits and its application to DC–DC converters

Top-level, transient, transistor-based simulations are a critical step in the product-development cycle of mixed-signal integrated circuits. These simulations are normally performed just before fabrication and unfortunately impose cumbersome bottlenecks in the design flow. Verification is an iterative process by nature, whereby each problem found requires another simulation to ensure a proper fix is in place, and because of the complexity of a large system, minor errors can cost days, increasing design time and time-to-market. A top-level transistor-based simulation strategy is proposed with minimal time overhead. The strategy is to start with a quick, all macro-model system simulation and gradually substitute one transistor-level sub-block at a time for each additional run. For optimal results, less computationally intensive blocks, which can be determined from a proposed set of screening simulations, are replaced first. The proposed strategy was tested and applied to a buck, current-mode switching regulator, and the results show that simulation overhead is least for linear analogue functions (e.g. op-amps) and worst for high-speed nonlinear circuits (e.g. signal generators). Nonlinear and bi-stable analogue blocks such as bandgap references take more time to simulate than op-amps and less than low frequency digital functions such as power-on-reset, which in turn are less intensive than ramp and pulse generators.