MAC Design Research Articles

EncodingNet: A Novel Encoding-Based MAC Design for Efficient Neural Network Acceleration

EncodingNet: A Novel Encoding-Based MAC Design for Efficient Neural Network Acceleration

Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs

Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs

Distributed V2X Sidelink Communications With Receiver Grant MAC Design

With the development of new radio (NR) technologies, sidelink (SL) transmission plays a more vital role in supporting low latency, higher reliability vehicle-to-everything (V2X) communications. Compared with the Long-Term Evolution (LTE), NR V2X aims to support enhanced V2X use cases with more stringent latency and reliability requirements. 3GPP introduces NR V2X distributed resource allocation to fulfill the low latency requirement to reduce the delay caused by requesting transmission resources from gNB. In distributed mode, UEs autonomously select resources without the scheduling from gNB. NR V2X introduces the physical sidelink feedback channel (PSFCH) to enhance transmission reliability. This paper presents the resource allocation mechanism for NR V2X distributed mode. Since the SL feedback channel is a new feature different from LTE V2X, we discuss the potential enhancements on resource allocation utilizing SL feedback channel to improve the reliability. This paper proposes a Receiver Grant-based resource allocation, which allows the receiver to send the grant with the feedback channel. By allowing the transmitter to indicate the pre-selected resources before the end of the previous reservation, the receiver can inform the transmitter about the collided resource selection through the PSFCH. The analytical models for NR V2X distributed mode with the feedback channel are also provided for UE to estimate the collision ratio. The simulation results and the analytical model show that the proposed Receiver (Rx) Grant-based resource allocation improves transmission reliability in terms of collision ratio. For future advanced V2X use cases, the analytical models provide an evaluation method and help UE make decisions to meet the reliability requirements.

Qualitative Analysis of dual MAC in Multihop Adhoc Wireless Network

Multihop adhoc wireless networks offer great challenges for protocol designers. Stations in such networks are constrained by factors like low power, limited bandwidth, link errors and collisions. Changes are needed at various levels of the protocol stack, most importantly at the media access layer(MAC). This paper emphasizes in minimizing the collisions, and take care of the hidden and exposed problems in multihop wireless networks. The MAC with Distributed Coordination Function(DCF)does not scale well in such networks. We introduce Point Coordination Function(PCF)in the region of high traffic areas, and discuss its effect on network performance. To improve network scalability and throughput, we propose the design of dual MAC. This work discusses architecture and working of the dual MAC. Performance results of the network using MAC are presented, and compared with that of pure DCF operation.

Energy Efficient MAC with VariableDuty Cycle for Wireless Sensor Networks

ABSTRACT WSN consists of many sensors, they need high throughput and network lifetime to get involved in communication. Duty Cycle is a key factor in sensor nodes to maintain sleep, active condition in the presence of overhearing, collisions of packets while data transmission between sensor nodes. The key challenge of sensor nodes is to attain high energy efficiency, throughput and low End-End Delay. This paper presents several of existing approaches for MAC protocol. They are (1) Synchronization between nodes (2) Mathematical Analysis (3) TDMA based MAC and (4) Cross-Layer Design. We proposed a new method for MAC protocol with variable duty cycle. Neighboring nodes follow same duty cycle and same active time. Far away nodes doesn’t maintain same duty cycle, hence their active time is not same. The duty cycle is maintained in synchronous way and adaptive manner among the nodes within the network. In this paper, a conventional MAC and proposed MAC are simulated using NS-2.35. Variable duty cycle approach in the proposed MAC with sleep and idle states for the nodes yields better throughput and energy efficiency with respect to other conventional technique. These results validate that the proposed variable DC-MAC is feasible for Wireless Sensor Network applications.

Vedic Arithmetic Based High Speed & Less Area MAC Unit for Computing Devices

Background: The rapid improvement in technology enables design of high-speed devices, with development of modified computational elements for FPGA implementation. With complexity increasing day-to-day, there is demand for modified VLSI computational elements. Basically, for the past decade an improvement in basic VLSI Operators like Adder, multiplier is significant. The basic multiplication operator is been completely refined in the aspects of FPGA implementation. Materials and Methods: This paper presents a design of 32-bit high-speed MAC unit based on Vedic computations. Among the many sutras of Vedic mathematics, by using the urdhvatriyagbhyam sutra the products are generated in parallel. This proposed technique results in multiplication step reduction. Results: The result shows that the proposed MAC unit, the number of steps required for multiplication and addition has been reduced, it leads to the decrease in area size. In comparison with the performance of existing method to proposed MAC, the LUT's are reduced by 50 percent. Conclusion: This paper comprehensively describes the basic Multiplication operation using urdhvatriyaghyam sutra for parallel multiplication process. Based on the Vedic sutras, the performance was analyzed on a hardware platform Spartan-3E Xilinx FPGA Device for a 32-bit MAC unit. The Implementation results shoes reduction in critical delay and area when compared to conventional booth multiplier-based MAC Design. Hence this works concludes that the proposed Vedic multiplier is suitable for constructing high speed MAC units.

A Novel Successive-Interference-Cancellation- Aware Design for Wireless Networks Using Software-Defined Networking

In traditional CSMA/CA-based MAC designs supporting successive interference cancellation (SIC), channel utilization is inefficient, because the inherited CSMA/CA-style contention approach often forces the whole channel to remain idle and the early released channel is not utilized. In this paper, we propose Multi-CQ, which is the first software-defined networking (SDN)-based MAC design for wireless LANs that supports SIC and significantly improves the channel utilization. Multi-CQ, adopting SDN’s functional separation idea and OFDMA, makes contention and data transmission be executed over two subchannels independently and concurrently, where the superposition coding are used for decoding combined signals, and multiple CQs (contention queues) are introduced to coordinate the concurrency. This concurrent execution greatly reduces the waste in channel contention. Next, adopting SDN’s central control idea, Multi-CQ controller selects nodes who can finish their frame transmissions in almost equal time, thereby improving the channel utilization. Finally, we develop a theoretical model to optimize bandwidth allocation for channel contention and data transmission. Extensive simulations verify the effectiveness of our design and the accuracy of our theoretical model. This study is also helpful to better design wireless MAC protocols supporting other advanced functionalities such as MU-MIMO.

Cooperation-Based Adaptive and Reliable MAC Design for Multichannel Directional Wireless IoT Networks

Internet of Things (IoT) is the ultimate enabler of modern civilization. Cooperative communication in multichannel directional wireless networks is one of the cutting-edge IoT research themes. Typically, cooperation in wireless networks is the opportunistic relaying of data packets for neighboring nodes by idle nodes. Current IoT-based researches related to multichannel with directional antenna introduce the control channel cooperation. But, the iterative phenomenon of negotiation in control channel results in higher communication delay. Hence, to reduce the data transmission delay, cooperation in data relaying need to be used along with control channel cooperation. In this paper, we propose a Cooperation-based Adaptive and Reliable MAC (CAR MAC) Design for Multichannel Directional Wireless IoT Networks that combines both of these cooperation and multichannel directional concepts of cooperation. Multichannel directional hidden terminal problems and deafness problems in medium access are solved using both concepts of cooperation jointly. Besides, multidirectional data packet relaying in the same data channel enables parallel transmission that increases the bandwidth utilization. Moreover, the proposed protocol uses a smart GPS (Global Positioning System) based neighbor discovery. Therefore, the directional position and distance among the IoT-enabled wireless nodes are smartly determined to make the control channel cooperation more informative. The results of extensive simulations reveal that CAR MAC achieves significant improvement in network performances.

Physical Layer and MAC Design for Self-Reliant Cognitive Multicast Networks Using LTE Resources

Existing Long Term Evolution (LTE) networks have untapped radio frequency resources, also known as white space, that can be repurposed for cognitive radio applications. A secondary network can opportunistically interweave communication within the white space of an existing LTE signal by leveraging cognitive radio. In this article, we present CIAO-LTE, a novel framework for forming a cognitive interwoven self-reliant secondary network with no additional physical infrastructure, collaboration from the existing primary network, and software or hardware changes in the primary LTE network. For medium access control, CIAO-LTE uses an adapted version of Slotted ALOHA with a no-back-off contention. We analyze parameter settings and conduct extensive simulations to validate performance. The simulation results show that CIAO-LTE achieves throughputs as high as 4.75 Mb/s on a 5MHz LTE signal and approximately 19Mb/s with a 20MHz LTE signal, and average packet delays within a few milliseconds.

Low Latency Prefix Accumulation Driven Compound MAC Unit for Efficient FIR Filter Implementation

This article presents hierarchical single compound adder-based MAC with assertion based error correction for speculation variations in the prefix addition for FIR filter design. The VLSI implementation of approximation in prefix adder results show a significant delay and complexity reductions, all this at the cost of latency measures when speculation fails during carry propagation, which is the main reason preventing the use of speculation in parallel-prefix adders in DSP applications. The speculative adder which is based on Han Carlson parallel prefix adder structure accomplishes better reduction in latency. Introducing a structured and efficient shift-add technique and explore latency reduction by incorporating approximation in addition. The improvements made in terms of reduction in latency and merits in performance by the proposed MAC unit are showed through the synthesis done by FPGA hardware. Results show that proposed method outpaces both formerly projected MAC designs using multiplication methods for attaining high speed.

A novel high speed Low Latency Column Bit Compressed MAC architecture for Wireless Sensor Network applications

Wireless Sensor Network (WSN) provides significant challenges for application such as distributed control and digital signal processing. Multiply-Accumulate Unit (MAC) plays a significant role in kernel computation which determines the speed and power factor of entire system. Constructing low power and high speed MAC is very critical to utilize VLSI technologies in WSN. This research work concentrates on fast, low power and reduced delay based Low Latency Column Bit Compressed (LLCBC) MAC. This proposed MAC design based on binary stacking counter is designed for optimizing delay, power, area and hardware complexities. Increased operational speed is attained by performing 6:3 and 7:3 binary stacking counters with higher column indeed of conventional full adder. The proposed method is simulated using cadence environment, in which superior outcomes are attained. The parameters such as Area, Cells, leakage power (nW), Dynamic Power (nW), Total Power (nW) and Delay (ps) are evaluated. For instance, in 16 bit, the proposed (LLCBC) MAC consumes 14.4% Area, 17.5% Total Power and 46.2% Delay with respect to maximum value among all MAC units compared. The proposed architecture is simulated, synthesized and place & route is done with 90 nm standard CMOS library using cadence SOC encounter, effectual improvement in terms of Power, Area, and Delay is attained.

Inter-Client Interference Cancellation for Full-Duplex Networks With Half-Duplex Clients

Recent studies have experimentally shown the gains of full-duplex radios. However, due to its relatively higher cost and complexity, we can envision a more practical step in the network evolution is to have a full-duplex access point (AP) but keep the clients half-duplex. Unfortunately, the full-duplex gains can hardly be extracted in practice as the uplink transmission from a half-duplex client introduces inter-client interference to another downlink client. To address this issue, we present the design and implementation of IC2 (Inter-Client Interference Cancellation), the first physical layer solution that exploits the AP’s full-duplex capability to actively cancel the interference at the downlink client. Such active cancellation not only improves the achievable capacity, but also better tolerates imperfect user pairing, simplifying the MAC design as a result. We build a prototype of IC2 on USRP-N200 and evaluate its performance via both testbed experiments and large-scale trace-driven simulations. The results show that, without IC2 , about 60% of client pairs produce no gain from full-duplex transmissions, while, with IC2 the median gain of the achievable rate over conventional half-duplex networks can be $1.65\times $ and $1.47\times $ for 1- and 2-antenna scenarios, respectively, even when clients are simply paired randomly.

A Survey of TDMA-based MAC Protocols for Vehicular Ad Hoc Networks

MAC design in a vehicle network is a challenging task due to high node speed, frequent topology changes, lack of infrastructure, and different QoS requirements. Several medium access control protocols based on Time Division Multiple Access (TDMA) have recently been suggested for VANETs in an effort to guarantee that all cars have sufficient time to send safety messages without collisions and to decrease the end-to-end delay and the loss ratio of packets. The reasons for using the collision-free media access control paradigm in VANETs are identified in this document. We then present a new topology-based classification and provide an overview of the MAC protocols suggested for VANETs based on TDMA. We concentrate on these protocols ' features as well as their advantages and constraints. Finally, we provide a qualitative comparison and address some open problems that need to be addressed in future studies to enhance the efficiency of TDMA-based MAC protocols for vehicle-to-vehicle (V2V) and vehicle to infrastructural (V2I) communications.

Reconfigurable and Traffic-Aware MAC Design for Virtualized Wireless Networks via Reinforcement Learning

In this paper, we present a reconfigurable MAC scheme where the partition between contention-free and contention-based regimes in each frame is adaptive to the network status leveraging reinforcement learning. In particular, to support a virtualized wireless network consisting of multiple slices, each having heterogeneous and unsaturated devices, the proposed scheme aims to configure the partition for maximizing network throughput while maintaining the slice reservations. Applying complementary geometric programming and monomial approximations, an iterative algorithm is developed to find the optimal solution. For a large number of devices, a scalable algorithm with lower computational complexity is also proposed. The partitioning algorithm requires the knowledge of the device traffic statistics. In the absence of such knowledge, we develop a learning algorithm employing Thompson sampling to acquire packet arrival probabilities of devices. Furthermore, we model the problem as a thresholding multi-armed bandit and propose a threshold-based reconfigurable MAC algorithm, which is proved to achieve the optimal regret bound.

Fine-Grained TDMA MAC Design toward Ultra-Reliable Broadcast for Autonomous Driving

In the autonomous driving era, V2X communication is essential since it enables rapid message dissemination via periodical beacon exchange (broadcast communication), which contributes to better situation awareness and maneuvering cooperation. However, designing a MAC protocol for reliable V2X broadcasting is challenging, as minimal beacon delivery delay and collision avoidance should be achieved simultaneously. In this article, we design a fine-grained TDMA-based MAC protocol to support ultra-reliable broadcast for autonomous vehicles. Specifically, three critical issues are first identified: mobility-caused time slot collision, time slot shortage, and stiff beacon rate limitation. Accordingly, three fine-grained solutions are provided to tackle those issues: mobility-aware time slot assignment, beacon rate adaption with safety awareness, and flexible beacon rates support. Moreover, a case study on mobility-aware time slot assignment based on road topology and lane distribution is presented, with simulation results' verification. Finally, we elaborate the steps to implement the fine-grained MAC protocol in autonomous driving environments.

Impact of Lossy Forwarding on MAC and Routing Design in Wireless Ad Hoc Networks

Multi-hop ad hoc networks may employ cooperative communication, in which opportunistic relays use the spatial diversity of radio channels to increase communication reliability. An emerging variant of traditional relaying and forwarding schemes is the lossy forwarding and joint decoding (LF-JD) concept. In theory, LF-JD has shown the potential to improve spectral efficiency, reduce transmit power, and decrease outage probability by exploiting route diversity and the broadcast nature of radio transmissions. To be applied in real devices, a lower-layer protocol stack embracing the LF-JD concept needs to be designed. In this article, we show how LF-JD impacts the design of MAC and routing protocols and whether its benefits translate to performance improvements. We show that, in comparison to currently available solutions, LF-JD can provide gains in scenarios with high interference or poor signal strength such as in V2V networks.

Full-Duplex MIMO Radios: A Greener Networking Solution

Relative to half-duplex (HD) radios, in-band full-duplex (FD) radios have the potential to double a link’s capacity . However, such gain may not necessarily extend to the network-wide throughput , which may actually degrade under FD radios due to excessive network interference. This paper identifies the unique advantages of FD radios and leverages multi-input multioutput (MIMO) communications to translate the FD spectral efficiency gain at the PHY level to the throughput and power efficiency gain at the network layer. We first derive sufficient conditions under which FD-MIMO radios can asymptotically double the throughput of the same network of HD-MIMO ones. Specifically, if a network of $2{N}$ HD radios ( ${N}$ links) can achieve a total throughput of dN bps (i.e., ${d}$ bps per link), then an FD-capable network with the same number of links and network/channel realization can achieve $2{N}$ ( $\textit{d}-1$ ) bps [i.e., ( ${d} -1$ ) bps per direction of a bidirectional link]. To leverage this theoretical gain, we exploit the “spatial signature” readily captured in the network interference to design an MAC protocol that allows multiple FD links to concurrently communicate while adapting their radiation patterns to minimize network interference. The protocol does not require any feedback nor coordination among nodes. Extensive simulations show that the proposed MAC design dramatically outperforms traditional CSMA-based and the non-orthogonal multiple access protocols with either HD or FD radios with respect to both throughput and energy efficiency. Note that in the literature, network interference is often treated as colored noise that then gets whiten during the signal detection process. However, through our MAC protocol, we emphasize that, unlike random noise, network interference has its own structure that can be “mined” for “intelligence” to better align the transceiver’s signal.

Evaluation of video payload over low latency networks: Flexilink

ABSTRACTBroadcast organisations need to handle both time deterministic traffic and best effort traffic. The adoption of packet networks allows a single converged network for handling both real-time (RT) media traffic as well as data traffic. Due to the historic pervasive growth of IP network, they are widely used to realise this converged network. However, they do have several drawbacks like big header size, software switching delays and inability to support multiple addressing schemes. To overcome these issues, solutions like traffic engineering, quality of service and over-provisioning are implemented in IP networks but has resulted in higher cost, power and system requirements. Flexilink network has been tested for audio payloads using simulation model and outperforms any existing RT network by providing an exceptional average end-to-end delay of microsecond range and a jitter below the audible threshold for live digital audio streaming. However, it is not tested for video payloads. A review of various networks used RT media distribution is included in this paper. The Flexilink architecture design modification to support the most widely used video formats such as MPEG-TS, MPEG-PS and SDI streams is explained. The average delay for multiple video streams over Flexilink is provided using simulation model. The recommendation for testing Flexilink using hardware is also explained in this paper.The Flexilink Mac design uses dual-buffer system to handle AF (asynchronous flow) and SF (synchronous flow) separately, with the Frame structure that supports current Ethernet frames.

An efficient MAC design for image processing application

Objectives: An efficient MAC design is planned for 2’s complement numbers with no more than partial-product creation methodology and diminution tree, whereas the succeeding step trappings an extraordinary sign-conservatory solutions. Methods/Statistical Analysis: Accumulate operations form an important process in signal and image processing applications. To expand MAC execution, the basic way postponement can be diminished by embeddings an additional pipeline register, either in the interior the two rows or stuck between the twos and the final adder. Findings: The 16 bit MAC architecture is implemented using Baugh-Wooley (BW) multiplier with Twin precision concept. The proposed methodology is verified by implementing in a 16 x 16 MAC unit. The performance parameters extracted demonstrates that the proposed Modified Booth with Twin precision based 16 bit MAC demonstrates an area reduction of 45.3%, delay reduction of 30.8% and power saving of 60% when compared to the MAC architectures designed using Baugh-Wooley with twin precision multiplier. Application/Improvements: It performs better than the conventional MAC in all the aspects. Keywords: Baugh-Wooley Multiplier, MAC Design, Partial-Product, Sign-Conservatory Solutions, Twin Precision

Optimization of Arithmetical Operators for the Enhanced Wallace Stage

<p>In the field of Digital signal processing (DSP), the reduction of some logical elements counts is one of the main considerations. To minimize the area, computational delay, and power, the digital form FIR filter is to be implemented. The optimization of the ATP (Area, Time and Power) is achieved by using the efficient multiplication and accumulation unit (MAC). In this work, the direct form FIR filter with the efficient MAC unit is presented. At the initial stage, the half adders and full adders are to be modified by the reduction of the logical gates. The modified half and full adder are implemented in the Wallace tree multiplier for performing the efficient multiplication process. Carry save adder is divided into the two stages to reduce the computational delay of arithmetical operators. The proposed MAC design is implemented in the direct form FIR filter by using the HDL language.</p>