LSI Circuits Research Articles

Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region

This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). This paper proposes an approximation-based implementation method for an MEP tracking system over a wide voltage region. This paper focuses on the MEP characteristics that the energy loss is sufficiently small even though the voltage point changes near the MEP. For example, the energy loss is less than 5% even though the estimated MEP differs by a few tens of millivolts in comparison with the actual MEP. Therefore, the complexity for determining the MEP is relaxed by approximating complex operations such as the logarithmic or the exponential functions in the MEP tracking algorithm, which leads to hardware-/software-efficient implementation. When the MEP tracking algorithm is implemented in software, the MEP estimation time is reduced from 1ms to 13µs by the proposed approximation. When implemented in hardware, the proposed method can reduce the area of an MEP estimation circuit to a quarter. Measurement results of a 32-bit RISC-V processor fabricated in a 65-nm SOTB process technology show that the energy loss introduced by the proposed approximation is less than 2% in comparison with the MEP operation. Furthermore, we show that the MEP can be tracked within about 45 microseconds by the proposed MEP tracking system.

Design and fabrication results of Z-gate layout MOSFETs for radiation hardness integrated circuit

A Z-gate layout MOSFET (ZLT) is expected to reduce the total ionizing dose effects which occur in the shallow trench isolation layer made of oxide. To verify the ZLT’s merit, the ZLT was designed and fabricated with the 0.18 μm standard CMOS technology. The ZLT was irradiated with 60Co γ-rays up to 10 Mrad, and its I–V characteristic fluctuation was compared with that of a standard straight gate layout MOSFET (SLT). As a result, it was confirmed that the Z-gate can suppress off-current fluctuations by 1/5, on-current fluctuations by 1/2 and threshold voltage fluctuations by 1/6 compared with the SLT. Since the size penalty of the ZLT is small, it is possible to improve the radiation hardness of the CMOS LSI circuit by just replacing SLTs with ZLTs.

Ion Accelerator Facility of the Wakasa Wan Energy Research Center for the Study of Irradiation Effects on Space Electronics

The core facility of the Wakasa Wan Energy Research Center (WERC) consists of three ion accelerators: a synchrotron, a tandem accelerator and an ion-implanter. Research on the irradiation effects using these accelerators has been performed on space electronics such as solar cells, radiation detectors, image sensors and LSI circuits. In this report, the accelerator facility and ion-irradiation apparatuses at WERC are introduced, focusing on the research on irradiation effects on space electronics. Then, some recent results are summarized.

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region

A method for runtime energy optimization based on the supply voltage (Vdd) and the threshold voltage (Vth) scaling is proposed. This paper refers to the optimal voltage pair, which minimizes the energy consumption of LSI circuits under a target delay constraint, as a Minimum Energy Point (MEP). The MEP dynamically fluctuates depending on the operating conditions determined by a target delay constraint, an activity factor and a chip temperature. In order to track the MEP, this paper proposes a closed-form continuous function that determines the MEP over a wide operating performance region ranging from the above-threshold region down to the sub-threshold region. Based on the MEP determination formula, an MEP tracking algorithm is also proposed. The MEP tracking algorithm estimates the MEP even though the operating conditions widely change. Measurement results based on a 32-bit RISC processor fabricated in a 65-nm Silicon On Thin Buried oxide (SOTB) process technology show that the proposed method estimates the MEP within a 5% energy loss in comparison with the actual MEP operation.

A Review on Increasing of Breakdown Voltage of Standard CMOS LSI Circuits by MEMS Post-Process

A Review on Increasing of Breakdown Voltage of Standard CMOS LSI Circuits by MEMS Post-Process

On the image formation in x-ray radiography using aligned carbon nanofibers

Evidence is presented that field electrons emitted from vertically-aligned carbon nanofibers (CNFs) yield clearer x-ray images than do thermionic electrons, under the identical electron-optical condition. Specifically, the same sample, an LSI circuit, mounted on the same x-ray chamber could be imaged far more sharply with a CNF emitter than with a thermionic one. It is hypothesized that electrons discharged from CNF tips hit the target to form “discrete focal points” thereon, thereby generating multiple x-ray beams that interplay to form a brilliant, sharply-delineated x-ray image. This hypothesis may stimulate open discussion on how to define the “focal point” for the x-ray imaging using nano-structured electron sources. Also, the improved resolution attained with CNFs might indicate that the heat generation originating in electron-target interactions is not so serious in the present field-emission mode.

Surge Protection for On-Hook and Off-Hook States of Communication Equipment Connected to the Telephone Networks

Telecommunications facilities with the advance of highly information-oriented society requires a higher transmission rate, LSI and VLSI circuits based on semiconductor technologies are widely used in communication devices. Modern microelectronic circuits may be susceptible to damage by lightning surges. Therefore, the protection of electronic circuits from lightning surges is highly interested. Applications of surge protective devices(SPDs) are to protect communication facilities from lightning surges. The operating characteristics of the telephone network are divided into the on-hook state and the off-hook state. A subscriber protector is normally installed telecommunication lines, but it limits the incoming lightning surges to the protection level of the on-hook state. Thus the protection of telephone from overvoltages in the off-hook state is not achieved. In this paper, in order to solve the above points, the hybrid surge protective circuit of protecting the telephone from overvoltages in off-hook and on-hook states was designed. The operating characteristics of the proposed surge protective circuit were experimentally analyzed and discussed.

Wafer-Level Vacuum Packaging by Thermocompression Bonding Using Silver after Fly-Cut Planarization

A novel wafer-level vacuum thermocompression bonding using electroplated Ag bonding frames which were planarized by diamond fly cutting was described. At relatively low temperature and press pressure, high shear strength and vacuum sealing were achieved. The diffusion of Ag into a Si substrate was suppressed by the implementation of a TiN barrier layer. Leak rate was measured by zero balance method was at approximately 3.6×10-14 Pa·m3/s. Therefore, the proposed process was useful for both wafer-level heterogeneous integration, such as the integration of MEMS and LSI circuits, and hermetic packaging for various microsystems.

Deterministic and nondeterministic failure models of LSI circuits exposed to radiation

Methods are proposed to estimate the relationship between probabilistic and order models for simulating functional failures of the large-scale integrated circuits (LSICs) based on Brauer’s fuzzy digital automaton and on a probabilistic automaton for reliability evaluation. In the first case, the behavior of the LSIC is determined by varying static and dynamic parameters; in the second case, by the statistical straggling of threshold failure levels.

SOIPIX R&D programme and applications

SOIPiX is a R&D project targeting the development of monolithic pixel detectors with Silicon On Insulator technology for future high energy physics experiments, X-ray experiments, and other applications. It integrates both radiation sensors and LSI circuits in one chip to achieve high resolution and intelligent detectors. After a short introduction about the advantages of monolithic active pixel sensors, the main characteristics of SOI monolithic sensors will be discussed: technological process, response to incident radiation and radiation hardness. Special attention will be given to the description of the so-called “back-gate” effect and the different techniques developed to mitigate it. Finally, various applications of this technology will be presented.

Novel Si Etching and Dielectric Liner Film Processing Technologies for Low-Cost TSV Packaging

In recent years, "2.5D silicon interposers" and "Full 3D stacked" technology for high-performance LSI circuits has attracted much attention since this technology can solve interconnection problems by using TSVs (Through Silicon Vias) to electrically connect stacked LSI circuits. 2.5D and 3D Si integration has great advantages over conventional 2D devices such as a high packaging density, small wire length, high-speed operation, low power consumption, and a high feasibility for parallel processing. Yet, the problem of cost-effective TSV production is still to be solved. In particular, the demand for a new plating bath technology to shorten the Cu plating time is pressing. In addition, TSV isolation liner materials will be necessary with lower cost for the production of future high-frequency devices. A new etch process has been developed for scallop-free and taper-shaped TSV fabrication [1]. By using a direct etch process instead of cycled etching, TSVs were obtained with smooth-sidewalls and tapered profiles. The absence of scallops has a positive effect on signal transmission speed. Also, the direct etch process allows for shorter TSV fill process times and thus provides lower cost of deposition processes like PE-CVD, PVD and Cu-ECP (electrochemical plating) [2,3]. A cost correlation of taper-shape etching and Cu-ECP (electro-chemical plating) will be included. For the TSV isolation, polyurea dielectric liners were successfully deposited using a vapor deposition polymerization technology (which is Ulvac’s FPF/PV large panel technology). This process allows for isolation liners in next-generation high-frequency devices and for the film formation into a TSV pattern. In summary, a novel low-cost TSV fabrication flow can be provided for 2.5 / 3D Si integration in high-frequency applications. The process flow yields scallop-free and taper TSVs, which can be filled effectively with electroplated copper and polyurea dielectric liners.

Application of probabilistic and fuzzy models to the simulation of radiation failures of LSI circuits

An approach to estimating the relationship between probabilistic and fuzzy models is proposed for simulating failures of large-scale integrated circuits (LSICs). These models are based on Brouwer’s fuzzy digital automaton and topological probabilistic models for estimating the functionality of digital devices. In the first case, the behavior of an LSIC is determined by the variation of deterministic static and dynamic parameters, and, in the second case, by the statistical dispersion of threshold failure levels.

Single-event-effect sensetivity characterization of LSI circuits with a laser-based and a pulsed gamma-ray testing facilities used in combination

Evaluation formulas are presented for equivalent heavy-ion linear energy transfer in the context of LSI-circuit sensetivity to single-event effects, based on local laser test data. The method suggested is validated for calculating the linear energy transfer from laser-pulse energy on the basis of radiation-response measurements on pulsed gamma-ray test sets. The method is free from errors related to the uncertainty in electrical properties of semiconductor structures.

Analysis of reliability test results for CMDS LSI and VLSI circuits

The reliability test results for CMDS LSI and VLSI circuits manufactured by Xilinx and Altera are analyzed. Upper estimates of failure rate with confidence probability P = 0.9 are obtained for all types of digital chips supplied by these companies.

The application of the analysis of potential driven particle diffusion to the strength of materials

The problems of diffusion in solid are widely treated as those of numerical analyses such as mechanisms of hydrogen diffusion which causes embrittlement, boundary micro crack initiation and growth under high temperature creep condition and stress and electro-migration due to vacancy diffusion in LSI circuit. In this paper, the significance of α multiplication method which we proposed to analyze the particle diffusion problems under potential gradient and the results obtained from this method were discussed for the problems of hydrogen embrittlement, vacancy diffusion which results in creep crack damage and deformation, and line failure in LSI circuit. Furthermore, temperature characteristic of the sensitivity of particle diffusion and concentration such as hydrogen and vacancy were discussed based on this proposed analysis.

Application of positron annihilation technique to front and backend processes for modern LSI devices

Developments of the semiconductor industry depend on ability to decrease the size of integrated circuits. Significant efforts to introduce new materials and their fabrication processes have been made in order to achieve such trends. However, one faces difficulties in the control of materials properties caused by atomic scale disorder. In the present paper, we used monoenergetic positrons to characterize ultra shallow junction formed on Si substrates and materials buried in LSI circuit structures. It was shown that the positron annihilation technique is a powerful characterization tool for modern Si-technology related materials.

Sequence Generator To Derive 8-Phase Variable Reluctance Stepper Motor

Literature survey indicates that the design of sequence generator is considered for a few number of control sequences of stepper motor. In our research a new circuit is built in a simple design for generation of all required sequences up to eight phases for Variable Reluctance (V.R.) stepper motor .This circuit must be followed by a power drive circuit to achieve the power requirement of the stepper motor. In case of getting a certain sequence , these data must be given to the system ; number of phases, number of 1st energized phases, type of sequence (full step or half step mode) and finally the direction of rotation, hence the system in response will generate the required sequence. Some papers previously used SSI & MSI circuits to build the sequence generator ,but in this paper an LSI (EPROM) circuit as well as SSI & MSI circuits are used to get minimal design with less components. The paper includes a brief description of the fundamentals of sequences controlling the stepper motor, the detailed proposed circuit description and samples of experimental results with an appendix illustrating a complete map of the EPROM which is used to store all required sequences.

Active Damping Using N4SID Model Referenced Predictive Anti-Phase Pitch Driving Method

Vibration suppression control considering elastic part deformation is one of the indispensable issues in the precision engineering field and a high-density LSI circuit processing[1]. This study aims at suppressing the induced vibration at rapid positioning operation using the N4SID (Subspace State Space model Identification) Model Referenced predictive Anti-phase pitch Driving Active Damping (N4SID-MRAD) and improve the positioning performance limit generated by conventional PID feedback control with existing actuator, which has low dynamic characteristics with a time lag. This control method consists of reduced order model identification (model order reduction using N4SID concept: offline process) and predictive control using the counter pitch driving based on the model output (: on-line process). This method was applied to principal axis vibration suppression of three axes positioning machine driven by a ball screw feeding mechanism to control the probe tip end positioning in feeding rod axis. The result showed that amplitude of residual vibration at the probe tip end suppressed with conventional PI controlled and the 77% performance improvement under low stable conditions that Balanced Realization could not be applied.

Developments of SOI monolithic pixel detectors

A monolithic pixel detector with 0.2μm silicon-on-insulator (SOI) CMOS technology has been developed. It has both a thick high-resistivity sensor layer and thin LSI circuit layer on a single chip. Integration-type and counting-type pixel detectors are fabricated and tested with light and X-rays. The process is open to many researchers through Multi Project Wafer (MPW) runs operated by KEK. Further improvements of the fabrication technologies are also under investigation by using a buried p-well and 3D integration technologies.

1112 オンライン部分空間モデル同定アクティブ制振制御(OS6-(1)オーガナイズドセッション《振動・音響・制御》)

Vibration suppression control considering elastic part deformation is one of the indispensable issues in the precision engineering field and a high-density LSI circuit processing. This study aims at suppressing the induced vibration at rapid positioning operation. This control method consists of reduced order model identification and Predictive Repeated control using the anti-phase pitch driving based on an estimated behavior of the identified model. This method improves the positioning performance limit generated by conventional PI feedback control with existing actuator, which has low dynamic characteristics with time lag. This study is to bring model identification in the online process and inspected the necessity of the online model.