Low Parasitic Resistance Research Articles

A selective-epitaxial-growth SiGe-base HBT with SMI electrodes featuring 9.3-ps ECL-gate delay

An ultra-high-speed selective-epitaxial-growth SiGe-base heterojunction bipolar transistor (HBT) with self-aligned stacked metal/in-situ doped poly-Si (IDP) (referred to as SMI) electrodes is developed. A 0.5-/spl mu/m-wide SiGe base self-aligned to the 0.1-/spl mu/m-wide emitter was selectively grown by using a UHV/CVD system. This self-aligned structure effectively reduces collector capacitance. In SMI technology, a tungsten film is selectively stacked on all poly-Si electrodes (base, emitter, and collector) in a self-aligned manner by using selective deposition without any heat treatment. So this technology does not cause unwanted diffusion of the base dopants and keeps a shallow intrinsic base profile. SMI technology can therefore provide low parasitic resistances and is well-suited to an SiGe-base HBT. A 2-/spl mu/m-wide BPSG/SiO/sub 2/ refilled trench was introduced in order to reduce the substrate capacitance. The low dielectric constant of BPSG/SiO/sub 2/ and the wide trench are very effective in reducing the sidewall element of substrate capacitance. This technology makes it possible to obtain ultra-high-speed operation with a 9.3-ps-gate-delay emitter-coupled-logic (ECL) circuit.

Low parasitic resistance contacts for scaled ULSI devices

Analysis of the components of parasitic series resistance in ULSI devices shows that interfacial contact resistivities less than 10−7 Ω cm2 will be required for sub 100-nm ULSI devices in order to stay on the historical performance trend. With dimensional scaling, the series resistance–width product decreases because channel lengths are scaled, while it increases in contacts because the contact length is decreased. Unless the contact resistivity is also reduced, the contact resistance ultimately becomes higher than the channel resistance, and no performance advantage will be obtained by making the device smaller. The challenge in meeting the contacting requirements in the 1997 National Technology Roadmap for Semiconductors is especially difficult in light of the desire to simultaneously contact both n+ and p+ junctions with a single material and given the trend towards lower processing temperatures, in which the equilibrium dopant electrical activity is lower. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentrations and minimizing contact barrier heights. Higher saturated drive currents, due to lowered parasitic series resistance, are observed in deep submicron devices made using silicides as diffusion sources (SADS); this technique eliminates the interfacial dopant segregation that is associated with conventional silicidation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity that normally accompanies silicidation; as a result, ESD devices give higher drive currents. The recrystallization of amorphous layers has been observed to result in non-equilibrium dopant activation which can be many times the equilibrium value. Finally, the use of heterojunction contacts using Si–Ge in the context of elevated source/drain devices presents another way to achieve lower contact resistance.

Quantized conductance in a small one-dimensional Si wire on a thin silicon-on-insulator substrate fabricated using SiN-film-masked oxidation

A new fabrication technique for a one-dimensional (1D) Si wire on a separation-by-implanted-oxygen (SIMOX) substrate, which is effective in reducing the parasitic resistance caused by the thin lead Si regions, is proposed. Thermal oxidation of the Si layer on which a stacked structure of and SiN films is formed does not reduce the thickness of the wide two-dimensional (2D) Si layer, though the 1D wire becomes thinner by the oxidation. A MOS-type 1D Si wire fabricated using this technique shows a clear step-like conductance as a function of gate voltage. Though the measured conductance step is slightly lower than the theoretically predicted value, it is much larger than previously reported values. The inherent conductance of the 1D wire can be extracted from the measured overall conductance owing to low parasitic resistance. The first conductance step thus obtained agrees well with the theoretical value of .

Metal Contact On Nitride Based Materials

ABSTRACTOwing to their large band gaps and high dielectric constants, III-V nitrides are very attractive for high temperature electronics and optoelectronic device applications. Improved material properties have recently led to a variety of devices being demonstrated such as blue, green, and yellow light-emitting devices as well as laser diodes, metal-semiconductor GaN based fieldeffect transistors (MESFETs), and AlGaN/GaN based high electron mobility transistors (HEMTs). The presence of parasitic resistance can significantly limit performance such as lower speed for electronic devices and higher turn-on voltage for the optical devices. There is room for improvements for both n- and p- type ohmic contacts in order to lower parasitic resistance and improve reliability. W based contacts on GaN and InGaN have been demonstrated and show excellent thermal stability, however the contact resistivity still in the range of 10−5 Ω-cm2. By using InN and graded InGaN as the contact layers, the contact resistivity can be reduced to ∼ 10−6 Ω -cm2.Besides low resistance ohmic contacts, a low leakage current and high turn-on voltage gate contact is critical to high performance electronic devices. Nitride based materials are very inert to conventional wet chemical etching used for other III-V compound semiconductors. Currently, dry etching is widely used for the device fabrication, however, III-nitrides are sensitive to dry etching, especially in the step of the gate recess etching. In this talk, metal insulator semiconductor (MIS) gate contacts based on AIN and Ga2O3/Gd2O3 will be discussed.

GaN based transistors for high temperature applications

We review theoretical and experimental results for GaN-based field effect transistors (FET) and discuss their potential for high temperature applications. We demonstrate that a decrease in ionized impurity scattering with an increase in temperature makes AlGaN-GaN DC-HFET to be superior candidates for high temperature applications. In these devices, a large sheet carrier concentration in the device channel allows us to obtain a relatively low parasitic series resistance and to achieve superior dc and ac performance (with the cutoff frequency times gate length product of 18.3 GHz × μm demonstrated recently by our group at room temperature).

Deep‐submicron CMOS technologies for low‐power and high‐performance operation

AbstractIntegrated circuits with 1GHz logic, 1G bit DRAM, and 1G transistors, together with the CMOS technology with a gate length of less than 0.2 μm are the ingredients of the “Giga‐Era.” However, in order to integrate these billions of MOSs at giga‐frequencies, the problem of the power consumption cannot be avoided. It is a common practice to cope with this problem by reducing the power supply voltage. In deep submicron MOS, although the basic gate delay is not likely to degrade as the power supply voltage is reduced, it is necessary to set a low threshold value (Vth) within the wafer plane with reduced parasitic devices, if the absolute current values become important, as in the interconnect load. However, reliability problems involving the short‐channel effect and hot carriers then cannot be avoided. This paper describes the use of the cobalt silicide process and shallow extension structure of the source/drain to reduce the parasitic resistance. It is also shown that setting a low Vth with fewer fluctuations is possible by combining the double‐side‐wall process and the counter‐dose process. By means of the above process, deep submi‐cron CMOS with low parasitic resistance and low Vth can be fabricated.

A multimode self-consistent model of the lasing characteristics of buried heterostructure lasers

Constricted mesa and buried heterostructure lasers have extremely wide modulation bandwidths due to their low parasitic capacitance and resistance and-because the structure provides very high confinement of both the carriers and photons in the active layer. The modulation bandwidth of these lasers is limited by current leakage effects and multilateral mode operation which both conspire to reduce the effective optical gain of the laser for a given operating current. These two problems are addressed and a fully self-consistent model of the lateral modal behavior and the current leakage problem in buried heterostructure lasers is addressed. The optical problem is solved using a modified version of the weighted index method, which provides a two-dimensional solution for optically active material with complex permittivity, and the onset of multimode behavior, where there is a superposition of two or more lateral modes, is also examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ultrafast operation of V/sub th/-adjusted p/sup +/-n/sup +/ double-gate SOI MOSFET's

To optimize the V/sub th/ of double-gate SOI MOSFET's, we fabricated devices with p/sup +/ poly-Si for the front-gate electrode and n/sup +/ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V/sub th/ of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects.

Metallized ultra-shallow-junction device technology for sub-0.1 μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 /spl mu/m MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability. >

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Growth of Pnp heterojunction bipolar transistor structures by metalorganic molecular beam epitaxy

Fabrication of high-quality Pnp heterojunction bipolar transistors has traditionally been difficult due to the inability to achieve and confine high p- and n-type doping levels using common dopants such as Be and Si. In this paper we discuss how carbon and tin can be incorporated during growth by metalorganic molecular beam epitaxy in order to produce Pnp structures. In particular it has been found that carbon introduced from trimethylgallium can be used to produce abrupt, thermally stable profiles in AlGaAs and that incorporation at concentrations up to mid-1019 cm−3 does not adversely affect the optical or structural quality of the material. In addition, we have found that the use of tetraethyltin (TESn) for tin doping of the GaAs base layer allows for higher doping and better confinement of the dopant than can be obtained with elemental Sn. Consequently, large-area (90-μm diameter) Pnp transistors fabricated from material grown with TESn show higher gain than those grown with elemental tin, in spite of the higher base dopant concentration. The gain obtained with TESn, 45, is the highest yet reported for an abrupt-junction, uniformly-doped Pnp structure. Furthermore, because of the low parasitic resistances which result from the use of carbon and tin doping, the I–V characteristics obtained in this study show superior performance relative to previously published reports.

Selfaligned AlGaAs/GaAs HBT grown by MOMBE

The very low parasitic resistance n-p-n GaAs/AlGaAs heterojunction bipolar transistors (HBT) grown by metal organic molecular beam epitaxy (MOMBE) using all gaseous source dopants are reported. The carbon and tin dopants were introduced through the uses of trimethygallium (TMGa) and tetraethyltin (TESn). To achieve the low parasitics, the graded InGaAs emitter cap layer was doped with tin to 5*10/sup 19/ cm/sup -3/ and the doping level in the subcollector was 3*10/sup 18/ cm/sup -3/. The emitter and collector sheet resistances were 25 Omega / Square Operator and 10 Omega / Square Operator , respectively. The 800 AA thick base layer was carbon doped to a level of 7*10/sup 19/ cm/sup -3/. The base contact resistance and sheet resistance were 0.1 Omega mm and 180 Omega / Square Operator , respectively. With a thin AlGaAs surface passivation layer for the emitter-base junction, the common emitter DC current gain was maintained up to 25, even for 2*5 mu m/sup 2/ emitter size devices. The unity short circuit current gain cutoff frequency f/sub T/, and maximum oscillation frequency f/sub max/, were 48 and 63 GHz, respectively.

Extremely high peak specific transconductance AlGaAs/GaAs heterojunction bipolar transistors

Self-aligned AlGaAs/GAs heterojunction bipolar transistors with peak specific transconductances as high as 25 mS/ mu m/sup 2/ of emitter area are discussed. These are the highest specific transconductances ever reported for a bipolar transistor. These devices, which contain no indium in the emitter, display specific parasitic emitter resistances of less than 1*10/sup -7/ Omega -cm/sup 2/. This low parasitic resistance is attributed to an improved n-type contact technology, in which a molybdenum diffusion barrier and a plasma-enhanced chemical vapor deposition SiO/sub 2/ overlayer are used to achieve low specific contact resistivities. >

A new fabrication technology for AlGaAs/GaAs HEMT LSIs using InGaAs nonalloyed ohmic contacts

The authors studied the nonalloyed ohmic characteristics of HEMTs (high electron mobility transistors). At high integration levels, nonalloyed ohmic contacts were found to have two advantages: an extremely short ohmic length with low parasitic source series resistance and direct connection between the source/drain and gate with the same metal. The propagation delay in a ring oscillator with a single-metal source/drain and gate formed simultaneously was 37 ps/gate (L/sub g/=0.9 mu m). The very short ohmic metal contacts and just three contact holes made it possible to reduce the memory cell area greatly. The cell is 21.5*21.5 mu m/sup 2/, one of the smallest ever reported for a GaAs-based static RAM. Using smaller load HEMTs or resistor loads in the memory cell, combined with nonalloyed ohmic technology with quarter- or subquarter-micrometer-gate HEMTs it is possible to fabricate a very-high-speed LSI such as a 64-kb static RAM with a reasonable chip size. >

Lateral PIN diodes for silicon-on-insulator monolithic microwave integrated circuits

Surface-oriented lateral mesa PIN diodes have been fabricated for the purpose of evaluating the feasibility of a silicon-on-insulator technology for microwave applications. For these devices, heavily doped p and n regions are formed from ion-implanted polysilicon diffusion sources which abut opposite sides of an intrinsic rectangular-shaped mesa, and electrical contact to the injecting contacts can be made with low parasitic series resistance. Devices for process evaluation were fabricated using a single-crystal silicon substrate (as opposed to recrystallized silicon-on-insulator films). Both d.c. and 3-GHz electrical characteristics indicate the desired conductivity modulation of the intrinsic region under forward bias. Moreover, the large breakdown voltage which is observed indicates that high peak-power handling capability should be possible.

Fabrication and performance of 0.1- mu m gate-length AlGaAs/GaAs HEMTs with unity current gain cutoff frequency in excess of 110 GHz

A multilevel resist process has been developed that is capable of producing 0.1- mu m T-cross-section gates using 50-kV electron-beam lithography. A ratio of upper to lower dimensions greater than three provides a low gate resistance of 450 Omega -mm, allowing improved microwave performance over high-resistance trapezoidal gates. Careful characterization and control of gate recessing resulted in less than 300 AA of ungated channel recess for minimal parasitic channel resistance. Several material structures were compared, varying the dopant incorporation from 80-AA spike doping to 40-AA spike doping to atomic planar doping. The growth of the spike-doped structures was optimized to provide a high n/sub s/>or=1.2 10/sup 12/ cm/sup -2/. In addition, these spike-doped structures had heavily doped caps of 100 Omega / Square Operator sheet resistivity to provide low parasitic source resistance. Performance was evaluated by on-wafer S-parameter measurements. The peak measured unity current gain cutoff frequency ranged from 90 to 113 GHz, depending on the material structure. This performance is attributed to careful attention to the details of gate formation, layer design, and MBE (molecular-beam epitaxial) growth.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A tunneling emitter bipolar transistor

We propose a new device-a Tunneling Emitter Bipolar Transistor (TEBT)-where the enhancement of the emitter injection efficiency is achieved by utilizing a very large difference in the tunneling probabilities for electrons and holes in a thin doped graded AlGaAs layer. This layer is inserted between the n-type GaAs emitter and p-type GaAs base. This device should have a high emitter efficiency and low parasitic resistances.

A new self-align technology for GaAs analog MMIC's

A new self-align technology suitable for fabrication of GaAs low-noise FET's and MMIC's is demonstrated. The present technology, which is based upon sidewall technology and pattern inversion technology, provides a negligible short-channel effect, a low-parasitic resistance and a well-controlled breakdown voltage, all of which are essentially required for high microwave performance. An experimental 0.5-µm gate FET fabricated using the new process exhibits a high transconductance such as 220 mS/mm and a low-noise figure such as 1.6 dB at 12 GHz.

Characterization of high-efficiency silicon solar cells

Preliminary results on silicon solar cells of improved performance recently have been described. The present paper describes the results of a more detailed optical and electrical characterization of these devices. The high performance of the cells is shown to be due to a high optical efficiency and near ideal junction characteristics combined with low parasitic resistance losses.

Microwave performance of 0.25-µm gate length high electron mobility transistors

The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-Å spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> of 65 GHz whereas wafer B gave an f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> of 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.