Low Voltage Power Supply Research Articles

Post-Fabrication Clock-Timing Adjustment Using Genetic Algorithms

To solve the problem of fluctuations in clock timing (also known as "clock skew" problems), we propose an approach for the implementation of post-fabrication clock-timing adjustment utilizing genetic algorithms (GAs). This approach is realized by the combination of dedicated adjustable circuitry and adjustment software, with the values for multiple programmable delay circuits inserted into the clock lines being determined by the adjustment software after fabrication. The proposed approach has three advantages: 1) enhancement in clock frequencies leading to improved operational yields; 2) lower power supply voltages, while maintaining operational yield; and 3) reductions in design times. Two different LSIs have been developed: the first is a programmable delay circuit, developed as an element of the clock-timing adjustment, while the second is a medium-scale circuit, developed to evaluate these advantages in a real chip. Experiments with these two LSIs, as well as a design experiment, have demonstrated these advantages with an enhancement in clock frequency of 25% (max), a reduction in the power-supply voltage of 33%, and a 21% shorter design time.

009 Evaluation of an Ozone‐Based Wound Management System

The onset of infection can lead rapidly to sepsis, septic shock, and eventually death. Considering the high costs of hospitalization and the added trauma and discomfort to the patient, improved methods for infection control are needed. Ozone offers a specific solution to the problem of effective management of microbial wound contamination. Despite the advantages, several technical barriers have prevented ozone‐based disinfection treatments from becoming more widely investigated. Negative press from years of unsubstantiated medical successes has made the medical community wary of even legitimate ozone technologies. Because there has been no research into using ozone in infection prevention, much of the hardware has not been developed to the stage where the technology can be used in clinical trials. Lynntech Inc., over the past 5 years, has been working to develop a pre‐clinical ozone‐based wound management system. This new hardware uses an electrochemical ozone generator that can deliver a predetermined quantity of ozone gas to a specific wound site. Electrochemically generated ozone has been shown to be effective against a range of gram negative and gram positive bacteria and our studies with various mimetic wound systems have shown that with controlled delivery, ozone can be utilized as either a disinfectant or as a biostat. The device is well suited for hospital use as it operates of low voltage power supplies and unlike other ozone generation technologies will not interfere with other electronic equipment while it is in operation. This paper outlines both the advantages and limitations of using an ozone based system as a wound management tool and looks to the future research that needs to be performed to substantiated the initial research findings.

CMOS Monolithic Metal–Oxide Sensor System Comprising a Microhotplate and Associated Circuitry

A gas sensor system fabricated in industrial CMOS technology is presented, which includes, for the first time, a microhotplate and the necessary driving and control circuitry on a single chip. Post-complementary-metal-oxide-semiconductor (CMOS) fabrication steps, such as micromachining of the membrane structure, the deposition of noble metal on the electrodes, and the processing of the sensitive metal-oxide layer, have been developed to be fully compatible with the industrial CMOS process. Temperatures up to 350/spl deg/C were reached on the hotplates using a low-voltage power supply (5 V). A symmetric hotplate design with a temperature homogeneity of better than 2% in the heated area was realized. The integrated temperature controller regulates the membrane temperature with a resolution of /spl plusmn/0.3/spl deg/C in the tracking mode. The temperature increase on the bulk chip owing to heat transfer through the membrane is less than 2% of the respective membrane operation temperature (6/spl deg/C at 350/spl deg/C membrane temperature). The gas sensing performance of the sensor was assessed by test measurements with carbon monoxide (CO). The gas tests evidenced a limit of detection of less than 5 ppm CO.

LHCb Silicon Tracker infrastructure

The LHCb Silicon Tracker is a vital part of the experiment. It consists of four planar stations: one trigger and three inner tracking stations. The operation of the Silicon Tracker detectors and electronics is provided by its infrastructure: cooling system, high- and low-voltage power supply systems, temperature and radiation monitoring systems. Several components of these systems are located in the experimental hall and subjected to radiation. This paper mainly concentrates on the recent development: requirements definition, evaluation of possible implementation scenarios, component choice and component radiation tests.

Multi-mode radiator panels

The invention relates to a system with multi-mode radiator panels used to reproduce sound. The multi-mode radiator panels include at least one driver, a core layer and two cover layers connected to the core layer. The panels are typically mounted in a frame with attachments providing a connection between the frame and the unit formed of the core layer and the cover layers. To protect the system against overload and damage, the entire driver electronics is housed in a hermetically sealed air space located between the frame, the core layer and the attachments. The driver electronics includes a power amplifier powered by low-voltage power supply. The voltage supply may be buffered by a battery to keep the average power supplied to the electronics small, while still being able to reproduce infrequently occurring peak power events. Buffering of the battery has the additional advantage that if the power supply is completely interrupted, the battery enables the sound reproduction to continue for a certain time in the event of a power failure, which is important for transmitting emergency announcements. The multi-mode radiator panels can also be connected via a bus, so that a single cable strand may be used to supply the acoustic signal and the electric power.

Minority carrier transport properties of GaInNAs heterojunction bipolar transistors with 2% nitrogen

GaAs-based heterojunction bipolar transistors (HBTs) have a relatively large turn-on voltage of approximately 1.4 V that can only be decreased by reducing the band-gap energy of the base material. For a variety of applications, particularly operation with low power supply voltage and reduced power dissipation, it would be desirable to have a smaller value of turn-on voltage. We report the performance of NpN double heterojunction bipolar transistors fabricated on a GaAs substrate with a Ga0.89In0.11N0.02As0.98 base that has a band-gap energy (Eg) of 0.98 eV; this is achieved with a nitrogen composition of 2%. These devices have a turn-on voltage VBE that is 0.4 V lower than that of their GaAs-base counterparts. The peak incremental current gain HFE is 8. The current gain of nitrogen containing HBTs is degraded due to the complex change in transport properties of carriers through the GaInNAs base region. In this article, the transport properties of GaInNAs-base HBTs are investigated by temperature-dependent dc current–voltage characteristics, optical and high frequency small-signal electrical measurements. The characterization of these devices is important to understand the effect of nitrogen on the device performance.

A new active common-mode EMI filter for PWM inverter

This paper presents a new active common-mode electromagnetic interference (EMI) filter for the pulse-width modulation (PWM) inverter application. The proposed filter is based on the current sensing and compensation circuit and it utilizes a fast transistor amplifier for the current compensation. The amplifier utilizes an isolated low-voltage DC power supply for its biasing and it is possible to construct the active filter independent of the source voltage of the equipment. Thus the proposed active filter can be used in any application regardless of its working voltage. The effectiveness of the proposed circuit has been verified by experimental results.

A low-voltage, versatile CMOS four-quadrant analogue multiplier

This paper describes a four-quadrant analogue multiplier circuit using a low-voltage power supply. It comprises two voltage/current adders and a basic multiplier. Its major advantages over other low-voltage multipliers are that it can operate on either a single power supply or two power supplies, and that its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects were analysed and the simulated results revealed that: (1) for a two-power supply voltage of 2 V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4 VP–P, the power dissipation is about 0.4 mW and the −3 dB bandwidth is more than 55 MHz; (2) for a single-power supply voltage of 2 V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4 VP–P, the power dissipation is about 0.2 mW and the −3 dB bandwidth is more than 55 MHz. Experimental results are provided to confirm the operation of the circuit.

Optimal decoupling capacitor sizing and placement for standard-cell layout designs

With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.

A CsI(Tl)-PIN photodiode gamma-ray probe

We characterize two single elements consisting of 10×10×5 and 5×5×5mm3 scintillator crystals read out by 10×10mm2 PIN silicon photodiode. The photodiode signal is amplified by an ultra-low-noise preamplifier and a pulse shape amplifier. The photodiode has a low leakage current (<1nA) and a small capacitance for electronic noise minimization. This probe demonstrates, at room temperature, an energy resolution of 15% for 140keV gamma rays and 8.38% for 365keV. Detection efficiency of a 57Co source placed at a distance of 1cm is 250countss−1μCu−1. Furthermore, the detector compactness, its low sensitivity to magnetic fields and the low-voltage power supply are very useful features for per-operative use.

Low power high dynamic range photomultiplier bases for the surface detectors of the Pierre Auger observatory

Design, tests and production methods of the photomultiplier bases for the surface detectors of the Pierre Auger Observatory are presented. The voltage divider is a purely resistive chain including a low consumption high voltage power supply. Two different output sensitivities have been obtained by using the anode and the last amplified dynode outputs. The charge ratio between the anode and the amplified dynode is around 32. The design ensures the stability of the gain and of the base line for events made of several pulses over a long time duration (up to 20μs) and a total charge ranging from a few to 6×105 photoelectrons (typical value: a few thousands) with a peak photocathode current of up to 200nA. The pre-production, test and mounting on photomultipliers of 200 bases has been carried out. The total production is 5000 pieces.

Monolithic RF bandpass track-and-hold

A new bandpass track-and-hold (BP-T/H) open loop architecture is developed as a single stage monolithic circuit with low voltage power supply. The sampling of 912 MHz RF-signal with 100 MS/s is demonstrated by Spectre-Cadence-4.4.6 simulations on 0.35 µm RF-SiGe/BiCMOS process of Texas Instruments.

Heterojunction bipolar transistors implemented with GaInNAs materials

Use of GaInNAs in the base of heterojunction bipolar transistors (HBTs) on GaAs substrates allows a reduction of the turn-on voltage, Vbe,on, of the devices, facilitating their use in applications with low power supply voltage (particularly battery operated power amplifiers for mobile communications). Using GaInNAs with N content below 2% and In content of 1–20%, HBTs have been demonstrated with Vbe,on values lower by 25–400 mV than those of conventional GaAs-based HBTs. The GaInNAs base regions exhibit lower diffusion length than conventional GaAs bases, which reduces current gain and detracts from high-frequency performance, as well as higher base sheet resistance. These adverse effects can be mitigated by proper design tradeoffs of base thickness and nitrogen composition, as well as by compositional grading in the base to provide a built-in quasi-electric field to assist electron transport.

A low-voltage wide-band CMOS precision full-wave rectifier

A simple integrable circuit for implementing a precision full-wave rectifier circuit in CMOS technology, which can be operated from a low-voltage power supply, is described. The realization method is based on the use of a MOS class AB configuration to improve the high frequency performance. The circuit exhibits a very sharp corner in the dc transfer characteristic. Simulation results showing the performance of the proposed circuit are also presented.

Proposal of Application of Pulsed Vision Chip for Retinal Prosthesis

A vision chip based on pulse frequency modulation (PFM) is proposed as a retinal prosthesis device for use in subretinal implantation. A pixel circuit of PFM has been fabricated using standard CMOS technology. A dynamic range of 40 dB is demonstrated at a low power supply voltage of 1 V. It is found that the competition between the charge current to the photodiode and the photocurrent affects the output pulse characteristics under the conditionds of low power supply voltage and strong light illumination. For in vitro and in vivo experiments, two methods of improving the PFM circuits are considered. One is controlling the pulse frequency. By adding one transistor to the PFM circuit, the output pulse frequency can be experimentally controlled by a factor of two. The other is using a biphasic output, which is required to keep a charge balance in a living body. By introducing differential circuits, the biphasic output has been confirmed by simulation.

First demonstration of monolithic InP-based HBT amplifier with PNP active load

An InP-based integrated HBT amplifier with PNP active load was demonstrated for the first time using complementary HBT technology (CRBT). Selective molecular beam epitaxy (MBE) regrowth was employed and a merged processing technology was developed for the monolithic integration of InP-based NPN and PNP HBTs on the same chip. The availability of PNP devices allowed design of high gain amplifiers with low power supply voltage. The measured amplifier with PNP HBT active load achieved a voltage gain of 100 with a power supply (V/sub CC/) of 1.5 V. The corresponding voltage swing was 0.9 V to 0.2 V. The amplifier also demonstrated S/sub 21/ of 7.8 dB with an associated S/sub 11/ and S/sub 22/ of -9.5 dB and -8.1 dB, respectively, at 10 GHz.

GaAs/Ga 0.89In 0.11N 0.02As 0.98/GaAs NpN double heterojunction bipolar transistor with low turn-on voltage

GaAs based heterojunction bipolar transistors have a relatively large turn-on voltage of approximately 1.4 V that can only be decreased by reducing the bandgap energy of the base material. For a variety of applications, particularly operation with low power supply voltage and reduced power dissipation, it would be desirable to have a smaller value of turn-on voltage. We report the DC performance of NpN double heterojunction bipolar transistors fabricated on a GaAs substrate with a Ga 0.89In 0.11N 0.02As 0.98-base that has a bandgap energy ( E g) of ∼0.98 eV. These devices have a turn-on voltage V BE that is 0.4 V lower than that of their GaAs-base counterparts. To overcome the large conduction band discontinuity between GaAs and Ga 0.89In 0.11N 0.02As 0.98 both chirped superlattice and delta doping were employed. Peak incremental current gain of h fe=8.5 was obtained.

A bitline leakage compensation scheme for low-voltage SRAMs

A bitline leakage current of an SRAM, induced by leakage current of the transmission transistors in the cells that are associated with the bitline, increases as the threshold voltage (V/sub TH/) of the transistors is reduced for high performance at low power-supply voltage (V/sub DD/). The increased bitline leakage causes slow or incorrect read/write operation of an SRAM because the leakage current acts as noise current for a sense amplifier. In this paper, the problem has been solved from a circuitry point of view, and the scheme which detects the bitline leakage current in a precharge cycle and compensates for it during a read/write cycle is proposed. Employing this scheme, the SRAM with 360-/spl mu/A bitline leakage current can perform a read/write operation at the same speed as one that has no bitline leakage current. This enables a 0.1-V reduction in V/sub TH/, and keeps the V/sub TH/ and delay scalability of a high-performance SRAM in technology progress. An experimental 8-Kb SRAM with 256 rows is fabricated in a 0.25-/spl mu/m CMOS technology, which demonstrates the effectiveness of the scheme.

Third-generation plasma immersion ion implanter for biomedical materials and research

A third generation plasma immersion ion implanter dedicated to biomedical materials and research has been designed and constructed. The distinct improvement over first and second generation multipurpose plasma immersion ion implantation equipment is that hybrid and combination techniques utilizing metal and gas plasmas, sputter deposition, and ion beam enhanced deposition can be effectively conducted in the same machine. The machine consists of four sets of high-efficiency metal arc plasma sources with magnetic filters, a custom designed high voltage modulator for operation up to 60 kV, a separate high-frequency, low-voltage power supply for hybrid treatment processes, special rotating sample stage for samples with an irregular shape, and other advanced features. The machine has been installed at Southwest Jiaotong University and operated reliably for 6 months. This article describes the design principles and performances of the machine as well as pertinent biomedical applications.

A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

Silicon-on-insulator (SOI) devices have the great advantage of high operating speed in low supply voltages. This paper presents megabit-class high-speed and low-power embedded SRAM techniques for high data-throughput CMOS/SIMOX ASICs. In order to reduce the power dissipation of high-operating-frequency SRAMs, the multi-V/sub DD/ scheme using a low-voltage power supply only for restricted functional blocks is proposed along with the voltage-swing-matching circuit for "low-voltage" blocks. A squashed double-density layout of six-transistor-type memory cell realizes a small size of 8.64 /spl mu/m/sup 2/ under a 0.3-/spl mu/m CMOS/SMOX logic process including LOCOS isolation and plain local interconnections (e.g., tungsten-deposited diffusion layer and pseudocontacts). A new resistor-coupled current-sense amplifier makes it possible to detect the small readout signal from the memory cell with a short sensing time. To shorten the writing time, each bitline has an individual writing driver (per-bitline architecture). The recovery time of bitlines lowered to write data is also shortened with an accelerator combined with the pulse-reset wordline. A 64 K-words/spl times/16-bits SRAM test chip, fabricated with the 0.3-/spl mu/m pseudomulti-V/sub th/ CMOS/SIMOX process (a short gate length of 0.2 /spl mu/m is available for the fully depleted MOSFETs), has demonstrated the 300-MHz operation under a typical condition with 2- and 1-V power supplies. The power dissipation in standby is less than 0.1 mW and that at 200-MHz operation with a modified checkerboard test pattern is 35.6 mW for single fan-out loads.