Low-voltage Organic Thin-film Transistors Research Articles

Achieving low-voltage operating high-mobility organic thin-film transistors by a multi-layered gate dielectric

Organic thin-film transistors (OTFTs) have attracted great attention for their inherent advantages and promising applications in emerging fields. Simultaneously realizing low-voltage operation and high-mobility in one OTFT is one of prerequisites for the commercialization, which is a huge challenge so far. An important route to address this challenge is to develop an ideal gate dielectric with a high capacitance and a low interfacial trap density at the dielectric/channel. In this Letter, we demonstrate the low-voltage operating high-mobility OTFTs by elaborately designing and processing a multi-layered gate dielectric. The gate dielectric consists of a high permittivity polymer film, a polymer buffing layer with a high surface energy, and an ultrathin long-chain alkane buffer layer. The effects of both the structures and the processes of gate dielectrics on the performances of OTFTs are investigated in detail. In addition, the relevant physical mechanisms are discussed. Finally, the optimal OTFTs exhibit high mobilities with the average and maximum values up to 5.62 and 6.74 cm2/V s, respectively, at low operating voltages below −5 V. Our findings reveal that designing and processing a reasonable multi-layered gate dielectric is a promising strategy to achieve both high-mobility and low-voltage operation in OTFTs, thereby fostering their development.

Hybrid CMOS and Pseudo-CMOS Organic Memory for Flexible Sensors

In this paper, we propose and elucidate a novel static random access memory (SRAM) for flexible electronic systems using low-voltage organic thin-film transistors. The SRAM can be used for local data storage and post-processing of the signals generated by sensors. This is essential for truly flexible systems. The proposed SRAM utilizes hybrid CMOS and pseudo-CMOS design to enhance stability. The memory cells based on CMOS design style utilize p-type access transistors to improve area efficiency and stability. A degradation-mitigation circuit, based on pseudo-CMOS design style, extends retention time. The proposed circuit, which is comprised of few basic logic gates, is easy to implement and occupies minimum layout area. The SRAM circuit can self-detect degradation and automatically perform a process to mitigate device degradation at the necessary time periods.We confirm the operation of key components in the proposed memory via test chip measurements. Additionally, the effectiveness of the degradation-mitigation circuit has been verified.

Aging-robust amplifier composed of p-type low voltage OTFT and organic semiconductor load

This paper proposes an amplifier circuit design suitable for low-voltage organic thin-film transistors (OTFTs). To overcome the issues common to low-voltage OTFTs, such as the yield, degradation, and performance differences between p-type and n-type TFTs, we design the circuit based on an inverter comprising only p-type transistors. The optimal bias voltage for the amplifier stage is provided through a bias circuit. The transistor performance degradation is compensated for by sharing the gate bias voltage (i.e. the main cause of degradation) between the bias and amplifier stages. In addition, an organic semiconductor is used as a passive load of the amplifier to reduce the area and failure probability. Test chip measurements demonstrate that the organic material operates as a resistor. The gain and cut-off frequencies of the proposed amplifier circuit can be adjusted by changing the size of the dinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]-thiophene resistor, providing a maximum gain of 27 dB. The proposed circuit can operate continuously for over 100 min without significant characteristic changes. The operation of the bias circuit, when applied to a differential amplifier design, is also verified. The differential amplifier achieves a maximum common-mode rejection ratio of 25 dB.

Behavioral modeling for low-voltage pentacene-based OTFTs and their implementations for organic logic circuits

We present a behavioral compact model and its implementation for low-voltage pentacene-based organic thin film transistors (OTFTs) using industry standard BSIM4 (Berkeley Short-channel IGFET Model) in LTspice platform. First, we simplify the number of BSIM4 model parameters according to the device structure. On the other hand, we adapt the BSIM4 mobility equation to OTFT and also involve the off-current using two behavioral current sources. Then, we perform metaheuristics-based optimization to extract the related BSIM4 model parameters together with additional four parameters, introduced in this work, fitting the modified model to the experimental data of an OTFT, using pentacene active layer. Finally, we implement the behavioral compact model in LTspice and validate its usage for low-voltage pentacene-based OTFTs comparing the experimental and modeled current–voltage curves. In this study, we also successfully simulate OTFT implementations of a Pseudo-E inverter, a Pseudo-E NAND gate, and a 1-bit full adder circuit based on NAND gates using our behavioral OTFT model and then investigate the static and dynamic performance parameters of these circuits. The supply voltage is 3 V and maximum frequency of the inputs is 500 Hz in the simulations.

Highly stable, low-voltage operable high-mobility flexible organic thin-film transistors based on a tri-layer gate dielectric

The application fields of organic thin-film transistors (OTFTs) depend on their field-effect mobility (μ). The low-voltage operation and good operating stability are the prerequisites for the practical applications of OTFTs. To date, it is still a huge challenge to obtain low-voltage operable OTFTs with high μ and good operating stability at the same time. In this work, we elaborately design and process a tri-layer gate dielectric, for pursuing the low-voltage operable, high-performance flexible OTFTs. The effects of the gate dielectrics on the device performances and the relevant mechanisms are discussed in detail. The tri-layer gate dielectric has a large gate capacitance per unit area, and simultaneously suppresses the polarization effect of the gate dielectric and the charge trapping at the interface and bulk of the gate dielectric, by which both the μ and the operating stability are significantly improved. As a result, the flexible OTFTs exhibit excellent figures of merit at low operating voltages below 4 V, with high μ up to 2.6 cm2 Vs−1, good bias stress stability with a negligible change of the channel current for 5000 s, and good mechanical flexibility with a negligible performance degradation after the tension bending for 1000 times at small curvature radii of both 5.0 mm and 3.0 mm in sequence. Our works provide a strategy for developing the high-performance flexible OTFTs with low-voltage operation, high μ and good operating stability simultaneously.

Temperature resistant amorphous polyimides with high intrinsic permittivity for electronic applications

High–dielectric–constant (high–k) polymers are highly desirable for high energy density capacitors and low–voltage organic thin-film transistors (OTFTs). However, conventional high–k polymers suffer from low temperature resistance or crystalline state, hampering their applications in electronic devices in general environments. Herein, by accurate monomer design and mild polycondensation, we synthesize a new polyimide (STP–PI) featuring amorphous state, intrinsic high–k, very high thermal stability, and self-standing properties. Having polar side groups and rigid twisty backbones, the STP–PI exhibits both high and stable permittivity (5.2 ∼ 6.0 from 1 MHz to 100 Hz) and excellent thermal stability (Td5% > 450 °C and Tg > 300 °C), superior to its counterpart without the polar side group. When applied for energy storage, STP–PI delivers a discharged energy density of 3.68 J cm−3 with discharge efficiency of 84% at 350 MV m−1 even at 200 °C, which makes a record among the state–of–the–art performance of instinct polymer dielectrics. When applied in low-voltage OTFTs as the dielectric layers, the devices show a low threshold voltage of −0.30 V and mobility value of 4.03 cm2 V−1 s−1. The design strategy paves a way of making high–k polyimides for high temperature energy storage and electronic applications.

Fröhlich polaron effect in flexible low-voltage organic thin-film transistors gated with high-k polymer dielectrics

The dielectric constant of the polymer insulator layer plays a key role in the charge transport and operation voltage of organic thin-film transistors (OTFT). However, the appropriate effects have not been well distinguished yet in donor-acceptor copolymer semiconductor-based OTFT. In this work, we demonstrate that the decreased mobilities in indacenodithiophene-co-benzothiadiazole OTFTs with the increase of gate dielectric constant is due to the Fröhlich polaron effect, especially for device gated with high-k relaxor ferroelectric polymer poly(vinylidene fluoride-trifluoroethylene-chlorofloroethylene). In order to eliminate this effect, a low-k polymer is introduced as a modification layer to construct a low-k/high-k bilayer dielectric to attain better mobility and improved bias stability. Finally, flexible top-gate OTFT is demonstrated on the polyethylene terephthalate substrate, showing good bending stability even after 1000 bending tests.

Flexible low-voltage organic thin-film transistors and PMOS inverters: the effect of channel width on noise margin

Low-operating-voltage (<2 V) organic thin-film transistors (OTFTs) and P-channel metal-oxide-semiconductor (PMOS) inverter circuits are fabricated on a 125 µm-thick flexible polyethylene naphthalate substrate using a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo[1,2-b;4,5-b′]dithiophene and polystyrene as an active p-type organic semiconducting material. All three electrodes (gate, source, and drain) are inkjet-printed, while the active semiconducting material is deposited by a dispenser system to achieve a saturation mobility of 0.32 cm2 V−1 s−1 at V GS = −2 V. Two different PMOS inverters are fabricated, for which the signal gain peak values are resolved for an ultra-low supply voltage, V DD = −0.5 V. We achieve a signal gain of 2.73 at V DD = −0.5 V. The effect of channel width is demonstrated for both OTFTs and PMOS devices. The ‘on’ current increases with channel width, and the switching point of the PMOS inverters shifts toward the middle of the voltage transfer characteristics, and hence improves the noise margin.

Potential of low-voltage organic transistors with high on-state drain current for temperature sensor development

Organic transistors with high on-state drain current at gate and drain voltages of −2 V fabricated on polyethylene naphthalate foils were investigated for sensor development. Two aspects were studied: (a) the ability of such transistors to raise the sensitivity of a temperature sensor and (b) the bias stress stability of the transistors subjected to square voltage pulses that turned them on and off repeatedly. To demonstrate the first aspect, the voltage-amplifying ability of the organic transistor was used to increase the response to the temperature, ordinarily achieved with a thermistor. To achieve voltage amplification, the transistor must have on-state drain current of at least 20 μA at gate and drain voltages of −2 V. Two transistors with on-state drain current of ~60 and ~120 μA were tested, leading to voltage gain of −2.8 and −4.9 V/V, respectively, thus increasing the sensitivity of the temperature sensor by a factor of up to 5. To study the second aspect, the same square voltage pulses were concurrently applied to the gate and drain electrodes, causing the transistor to turn on and off repeatedly. The turn-on and turn-off voltages were −2 and 0 V respectively and four different pulse periods were used: T of 5, 20, 40 and 60 s. For each T , 1000 pulses with turn-on time of 1 s and varying turn-off times were applied to the transistors, leading to the aggregate net stress time of 1000 s in all cases. The changes in the on-state drain current, threshold voltage, and field-effect mobility depended on T , in spite of the net stress time being the same. The reduction in the on-state drain current did not exceed 17%, stabilization was also observed after about 500 cycles in some cases, and the maximum drop occurred for medium T , thus making T = 60 s a favorable condition for sensor operation. • Fabricated low-voltage organic thin-film transistors (OTFTs) on PEN. • OTFT on-state drain current at gate and drain voltages of −2 V is ~0.1 mA. • OTFT gain of ~5 V/V achieved, raising the response to temperature by a factor of 5. • Pulsed bias stress investigated to turn the OTFT on and off repeatedly. • On-state drain current stabilization observed in some cases.

Stable organic SRAM cell with p-type access transistors

This paper demonstrates the implementation of a static random access memory (SRAM) cell that is suitable for low-voltage organic thin-film transistors (OTFTs). SRAM is an essential component in electronic systems which can store data or instructions for various applications. We use p-type OTFTs for the access transistors to gain higher areal efficiency and better robustness than those of conventional OTFT-based SRAM construction. We verify the stability of the proposed SRAM cell and optimize the transistor sizes through SPICE simulation. Using test chip measurement, the correct write/read operation of the proposed SRAM cell is confirmed under a 10× imbalance of the on-current ratio. The proposed SRAM cell achieves a 50% area reduction and a 2.5× static noise margin improvement, compared to the existing OTFT SRAM cell design.

Correction: Large-area printed low-voltage organic thin film transistors via minimal-solution bar-coating

Correction for ‘Large-area printed low-voltage organic thin film transistors via minimal-solution bar-coating’ by Sujin Sung et al., J. Mater. Chem. C, 2020, 8, 15112–15118, DOI: 10.1039/D0TC03089A.

Interface Engineering With Polystyrene for High-Performance, Low-Voltage Driven Organic Thin Film Transistor

We report a solution-processed, high-performance organic thin-film transistor (OTFT), using polystyrene (PS) as interlayer with the semiconducting material P2TDPP2TFT4 as an active layer. We achieved a significant improvement employing the PS as an interlayer between the P2TDPP2TFT4 and ${{{\text {AlO}}}}_{X}$ gate insulator. The filed-effect mobility ( $\mu _{{{\text {FE}}}}$ ) and ON/OFF current ratio ${(}{I}_{{ \mathrm{\scriptscriptstyle ON}}}/{I}_{{ \mathrm{\scriptscriptstyle OFF}}}{)}$ reached to $0.82\,\,{{{\text {cm}}}}^{{{{2}}}}{\cdot } {{\text {V}}}^{{{-{1}}}}{\cdot } {{\text {s}}}^{{{-{1}}}}$ and ~105, respectively, which is higher than the devices fabricated with commonly used self-assembled monolayer (SAM) octadecyltrimethoxysilane (OTS) modified substrate under similar experimental conditions. Further analysis of the modified gate insulator utilizing atomic force microscopy, X-ray diffraction, and contact angle measurement revealed that smoother surface and lower surface energy were achieved by employing PS interlayer, which leads to more compatible surface energy with the semiconductor and interfacial trap passivation. Passivation of interfacial traps and lower surface energy using PS interlayer leads to the highly stable device performance, suggesting its application as a new interlayer with ${{{\text {AlO}}}}_{X}$ gate insulator to improve device performance.

Large-area printed low-voltage organic thin film transistors via minimal-solution bar-coating

Large-area printed low-voltage organic thin film transistors are fabricated with the bar-coating of minimal solutions of cross-linked dielectric and organic semiconductor.

UV-Cured Hafnium Oxide-Based Gate Dielectrics for Low-Voltage Organic and Amorphous Oxide Thin-Film Transistors.

In this study, we have fabricated hafnium oxide dielectrics for low-voltage organic and amorphous oxide thin-film transistors (TFTs) via a facile low-temperature solution method and investigated the electrical properties of these dielectrics. Hafnium oxide dielectric films can be easily fabricated by a sol-gel solution method and ultraviolet (UV) curing at room temperature. In addition, the surface energy of hafnium oxide films can be easily modified by using phosphonic-acid-based self-assembled monolayers. This modification makes these films compatible with organic semiconductors fabrication methods. These novel dielectrics exhibit excellent insulating properties (leakage current densities of <10-6 A/cm² at 2 V), high capacitances (up to 690 nF/cm²), and smooth surfaces (root-mean-square roughness <0.5 nm). Consequently, hafnium oxide-based dielectrics can be integrated into both pentacene-based and indium oxide-based TFTs, functioning at relatively low voltages (<±3 V) to achieve good performance (hole mobility: 0.31 cm²/V · s, electron mobility: 1.54 cm²/V · s, and on/off current ratios: >105).

Low-voltage organic thin-film transistors based on [n]phenacenes

Abstract Low-voltage p-channel organic thin-film transistors based on [n]phenacene (n = 5, 6 or 7) were fabricated on glass and on flexible poly(ethylene 2,6-naphthalate) (PEN) substrates. For the first time, these phenacenes were combined with two ultrathin gate dielectrics based on aluminium oxide and a monolayer of octadecyl-phosphonic acid in three different transistor structures. Regardless of the substrate and the transistor structure, the field-effect mobility is found to increase with increasing length of the conjugated [n]phenacene core, leading to the best performance for [7]phenacene. The largest average field-effect mobility we have obtained is 0.27 cm2/V⋅s for transistors on glass and 0.092 cm2/V⋅s for transistors on flexible PEN.

Feasibility of a low-power, low-voltage complementary organic thin film transistor buskeeper physical unclonable function

This paper demonstrates an implementation of physical unclonable function (PUF) using complementary organic transistors operating at low-voltage. PUF is an essential security element, and is important for various applications of organic devices. We implement a simple buskeeper PUF, which consists of two inverters. We confirm that the PUF bit values on the test chip can be read at a standard voltage for electronic circuits (3.3 V) via a standardized circuit board interface. We observed a low static current consumption (11.8 μA/90 bits) for the PUF chip. The PUF performance, chip-to-board interface performance, and requirements for the board interface in an organic transistor chip are discussed based on the measurement results of the test chip.

Micropatterned elastic ionic polyacrylamide hydrogel for low-voltage capacitive and organic thin-film transistor pressure sensors

Electronic skins (E-skins) have attracted great research interest because of their promising applications in stretchable optoelectronics, soft robotics, and personalized healthcare devices. However, it remains a great challenge to fabricate E-skin devices that meet strict practical requirements such as high sensitivity, low-power operation and noise-proof ability. Here, we developed a novel elastic ionic polyacrylamide hydrogel (EIPH) with a high capacitance for the development of low-voltage organic thin-film transistor (OTFT) pressure sensors. The EIPH was prepared by photopolymerization of an acrylamide monomer in an aqueous solution of poly (acrylic acid) and CaCl2 and was then in situ micropatterned on an indium-tin oxide electrode. The fabricated capacitive sensor with 10-µm-wide EIPH micropillar structures achieved a high sensitivity of 2.33 kPa−1 with a capacitance sensitivity of 103.8 nF/kPa. This capacitance sensitivity is more than 100 times higher than that of conventional capacitive pressure sensors due to the formation of an electrical double layer. The micropatterned EIPH was adopted as a dielectric layer in the fabrication of the OTFT-based pressure sensors. Such an EIPH-based OTFT pressure sensor not only greatly enhanced the sensitivity, i.e., 7.7 times higher than its capacitive counterparts, but also largely reduced the operation voltage to 2 V.

Room-temperature solution-processed, ZrOx-based hybrid gate dielectrics for low-voltage organic thin-film transistors on plastic substrates

For advanced electronic device applications including printable, flexible organic electronics and bioelectronics, it is crucial to develop novel dielectric materials with high dielectric strength and low-temperature processability compatible with plastic substrates for producing flexible and low-voltage organic thin-film transistors (OTFTs). Herein, we report the facile fabrication of rationally designed, high-capacitance hybrid gate dielectric films for low-voltage OTFTs on plastic substrates via a room-temperature solution process. To create room-temperature-processed gate dielectrics with high dielectric strength, we designed organic-inorganic hybrid gate dielectric films by including ZrOx networks as inorganic high-k oxide materials for obtaining large capacitance and 1,6-hexanediol diacrylate as a bifunctional UV cross-linking agent and a flexible organic component for increasing the density and flexibility of films and ensuring room-temperature processability. The UV cross-linked ZrOx-based hybrid composite films with a 15 nm thickness showed excellent dielectric properties with a leakage current density of ∼10−6 A/cm2 and a capacitance of 640 nF/cm2. The film surfaces were modified with hydrophobic self-assembled monolayers to match the surface energy of organic semiconductors for enhancing the OTFT performance. The utility of the hybrid dielectrics for flexible OTFTs was demonstrated by realizing pentacene TFTs on plastic substrates with a low operating voltage at –2.5 V, a high on/off current ratio of 105, a threshold voltage as low as –0.7 V, and a hole mobility up to 0.47 cm2 V−1 s−1, which are comparable to those performed on Si substrates.

High-k polymer materials containing cyclic carbonate as gate dielectrics for application in low-voltage operating organic thin-film transistors

Low-voltage operating OTFTs have attracted interest as core components for low power applications and electronics. An ideal insulation material as the OTFT gate dielectric layer should possess high-k, good insulation property, mechanical flexibility and inherent nature suitable for growth of organic semiconductors.

Low-Voltage, Flexible, and Self-Encapsulated Ultracompact Organic Thin-Film Transistors Based on Nanomembranes.

Organic thin-film transistors (OTFTs) are an ever-growing subject of research, powering recent technologies such as flexible and wearable electronics. Currently, many studies are being carried out to push forward the state-of-the-art OTFT technology to achieve characteristics that include high carrier mobility, low power consumption, flexibility, and the ability to operate under harsh conditions. Here, we tackle this task by proposing a novel OTFT architecture exploring the so-called rolled-up nanomembrane technology to fabricate low-voltage (<2 V), ultracompact OTFTs. As the OTFT gate electrode, we use strained nanomembranes, which allows all transistor components to be rolled-up and confined into a tubular-shaped tridimensional device structure with reduced footprint (ca. 90% of their planar counterpart), without any lossof electrical performance. Such an innovative architecture endows the OTFTs high mechanical flexibility (bending radius of <30 μm) and robustness-the devices can be reversibly deformed, withstanding more than 500 radial compression/decompression cycles. Additionally, the tubular device design possesses an inherent self-encapsulation characteristic that protects the OTFT active region from degradation by UV-light and hazardous vapors. The reported strategy is also shown to be compatible with different organic semiconductor materials. All of these characteristics contribute to further extending the potentialities of OTFTs, mainly toward rugged electronics.