Low-voltage Operational Amplifier Research Articles

Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application

CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

0.5-V High Linear and Wide Tunable OTA for Biomedical Applications

This paper presents a low-voltage nano-power multiple-input operational transconductance amplifier (MI-OTA) with high linearity performance and increased input voltage swing. The enhanced performances are achieved thanks to employing several techniques as the bulk-driven, source-degeneration, self-cascode and negative conductance along with the concept of the input signal attenuation formed by multiple-input MOS transistor. The MI-OTA is widely tunable that serves for biological signals processing. A 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> -order Butterworth band-pass filter (BPF) for electrocardiogram (ECG) signal processing with 55.8 dB dynamic rang is presented. The MI-OTA circuit is designed for 0.5V voltage supply and offers a 0.22% total harmonic distortion (THD) for 0.2V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> input signal with total power consumption of 13.4nW. Extensive simulation results including Monte Carlo analysis and process, voltage, temperature (PVT) corners using the 0.18μm CMOS technology from TSMC confirm the characteristics of the proposed MI-OTA and the filter.

Nanopower multiple-input DTMOS OTA and its applications to high-order filters for biomedical systems

A new solution for a low-voltage multiple-input dynamic threshold operational transconductance amplifier (MIDT OTA) for low-frequency signal processing applications is presented. The differential pairs of the proposed OTA combine, for the first time, the multiple-input MOS technique along with the dynamic threshold voltage MOS to achieve a very simple and power-efficient CMOS structure with increased total transconductance. Further, the proposed MIDT OTA has been used to realize a fifth-order low-pass filter (LP) and a sixth-order band-pass filter (BP) using coupled-biquads. The proposed OTA and the filter applications are supplied with 0.5 V and consume 5 nW and 25 nW, respectively. The input band pass filter noise is 82.76 µV, while the dynamic range is 59.5 dB for the third intermodulation distortion (IMD) of 2%. The proposed circuits were designed in a 0.18 µm TSMC technology, and validated by simulations using Cadence platform.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

A new low-voltage operational transconductance amplifier with push-pull CMFB scheme for low-pass filter applications

This paper proposes a new common-mode feedback (CMFB) scheme for a fully differential operational transconductance amplifier (OTA) with enhanced linearity and large voltage swing. The main feature is that the common-mode feedback circuit output with push-pull scheme, which is parallel to the high-side PMOS and low-side NMOS of the output stage, to stabilize the common-mode state quickly and to maximize the output voltage swing. In addition, the third-order Butterworth low-pass transconductance–capacitance filter based on linear transformation techniques is also implemented in the TSMC 0.18 µm 1P6M CMOS process. The power dissipation of the designed transconductance cell is only 161 μW and the average power consumption of this chip is 1.4 mW under 1.2 V supply voltage. The filter core occupies a silicon area of 0.044 mm2.

Design and simulation of tunable low-pass Gm-C filter with 1 GHz cutoff frequency based on CMOS inventers for high speed telecommunication applications

A tunable low-pass Gm-C filter with 1 GHz cutoff frequency is presented. The core of this filter is a high frequency low voltage operational transconductance amplifier (OTA) in which CMOS inverters...

A design of an ultra low-power operational transconductance amplifier

This paper describes a design of an ultra low-power, low-voltage operational transconductance amplifier (OTA). A two stage OTA is implemented in 0.13 μ m SiGe BiCMOS technology. The OTA operates with all transistors active in subthreshold region. Under the typical operating conditions, circuit supply voltage is 0.5 V, supply current 150 nA and power consumption is 75 nW. Low-frequency gain is 53 dB, gain-bandwidth product (GBW) 350 kHz and phase margin 55°. -1 dB gain compression point is -7.4 dBm and output intercept point (OIP3) -21.5 dBm. OTA layout active chip area is 0.0014 mm2.

1V Differential Input Stage with Bulk-Driven Current Mirror for Low-Voltage Operational Amplifier

Objectives: This paper presents the design and analysis of differential input stage to design low voltage operational amplifier, where bulk-driven MOSFETs are incorporated in the current mirror. Methods/Analysis: To be possible to operate circuit at lower supply voltage, body-driven transistors are used to design current mirror. Circuit is designed using 180nm (Complementary Metal Oxide Semiconductor) CMOS n-well technology and BSIM 3v3 Specter models are used to analyze the design. Performance parameters are validated by simulations. Findings: The amplifier shows DC openloop gain of 44 dB. The Unity Gain Bandwidth (UGB) is 3.3 MHz with a phase margin of 87.8°. The amplifier exhibits Common-Mode Rejection Ratio (CMRR) of 62 dB. The input referred spot noise voltage at 1KHz is 42.46nV/√Hz. These results are obtained with a supply voltage of 1V. Average power consumption of the amplifier is 36.36 μW under 10 pF load condition, which makes it suitable for low voltage and low power applications. Improvement: Gain can be further improved by employing cascode current mirror in the presented amplifier as it will increase output impedance. Keywords: Analog and Mixed-signal system, Bulk-driven Current Mirror, Differential Input Stage, Low-voltage Operational Amplifier, CMOS

Design of a low voltage low power self-biased OTA using independent gate FinFET and PTM models

In this paper a low power low voltage operational transconductance amplifier has been designed using IGFinFET. Pseudo differential pair and self-biased techniques have been used for rail-to-rail input operation of the OTA. The new technique used in this paper has the advantage of bulk-drive technique for low voltage analog designs without bulk-drive limitations. Using double gate FinFET, one gate has been used to adjust threshold voltage, while the input signal is applied to the other gate. Optimum gm and ro have been investigated for different gate configurations of the IGFinFET. Power consumption of the IGFinFET circuit is lower than its CMOS counterpart and shows good merits for analog design in analog and mixed signal applications. DFC method has been used for frequency compensation that needs smaller capacitors. Predictive Technology Model (PTM) 20nm IGFinFET has been employed for HSPICE simulations. The designed amplifier has 39.27dB gain with 45.05° phase margin and unity-gain bandwidth of 8.26MHz with 37.75μW power dissipation from a single 0.5V power supply.

Design and Simulation of a Low-Voltage Low-Offset Operational Amplifier

In many applications, offset of the OP-AMPs should be canceled to high accuracy be accomplished. In this work, an asymmetrical differential input circuit with active DC offset rejection circuit was implemented to minimize the systematic offset of the amplifier. The proposed OP-AMPs show that the systematic offset voltages is less than 80 µV.

Low-voltage bulk-driven OTA with enhanced transconductance and dc gain

A novel low-voltage bulk-driven operational transconductance amplifier (OTA) with enhanced transconductance and dc gain is presented. Based on the current-recycling structure and partial positive feedback technique, the effective transconductance of the bulk-driven input stage is improved. Also, the bulk-biasing technique is proposed to the composite transistor to achieve the dc gain enhancement. The proposed OTA is designed to operate with a 1 V supply using the CSMC 0.18 µm CMOS process. Results confirm that the gain–bandwidth achieves 29.6 MHz and the dc gain is higher than 86.1 dB when the load is 25.0 pF. The figure of merit is above 370, which demonstrates the proposed OTA has a significant boost compared to prior arts.

Low-voltage high-gain large-capacitive-load amplifiers in 90-nm CMOS technology

Low-voltage and low-power multistage operational transconductance amplifiers with new and efficient gain boosting and frequency compensation schemes are proposed in this paper. The presented amplifiers are designed to drive large capacitive loads with small power consumption at low-voltage supplies. The compensation schemes exploit a single Miller capacitor and an active feedback to form the main negative feedback loops for pole splitting and two feedforward paths. The new gain boosting technique discussed here improves the dc gain with negligible effect on the frequency response. The analysis and design procedures are discussed and the performance enhancements of the amplifiers are verified. The proposed OTAs have been implemented in a standard 90-nm CMOS process and the post-layout simulation results are reported. The amplifiers consume 8.7μW and 8.1μW at 0.5-V supplies and achieve 12.65MHz and 2MHz gain-bandwidth products while driving 150-pF and 15-nF capacitive loads, respectively.

A High-Gain and Low-Noise 0.9 µW Operational Amplifier

A low-voltage, low-power, high-gain and low-noise operational transconductance amplifier (OTA) by modifying conventional one is presented and analyzed. Design strategies are discussed for minimizing noise and increasing gain. The simulation results show that the open loop gain is improved from 68 dB to 74 dB and the input referred noise is also reduced from 926 / nV Hz to 475 / nV Hz . This amplifier operates at 0.8 V power supply voltage with a power consumption of 0.9 µW. All the simulations are obtained by using Hspice tool with 0.18 µm CMOS TSMC parameters.

Design of 0. 13um CMOS Low Voltage Rail to Rail Fully Differential Operational Amplifier Review

An operational amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage and low power operational amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense. One of the most important features in low voltage amplifier designs is ensuring that the amplifier maintains constant behavior in the presence of rail-to-rail input common mode variations while providing a rail-to-rail output to maximize signal-to-noise ratio. As the supply voltage to a standard CMOS op-amp is reduced, the input common mode range and the output swing get reduced drastically. Special circuits have to be used to raise them up to rail-to-rail supply voltage. In this work we propose a design of a low-voltage CMOS rail-to-rail folded cascode operational amplifier to be realized in a standard 130 nm CMOS technology with 1.2V supply voltage and consumes power less than 400uW. A two stage miller compensated folded cascode op-amp has a UGB >10MHz and achieves a gain >80dB over almost full range of the common mode input voltage.

0.5‐V bulk‐driven CMOS operational amplifier

A new solution for a low-voltage bulk-driven CMOS operational amplifier is presented in this study. The amplifier is designed using 50 nm process parameters and optimised for 0.5 V supply voltage. The circuit consumes 100 μW, performing 74 dB open-loop gain, 59 nV/Hz1/2 input referred noise at 1 MHz and 4.8 MHz gain bandwidth product (GBP) for 20 pF load capacitance.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

A Novel Low Voltage, Low Power and High Gain Operational Amplifier Using Negative Resistance and Self Cascode Transistors

In this work a low power, low voltage and high gain operational amplifier is proposed. For this purpose a negative resistance structure is used in parallel with output to improve the achievable gain. Because of using self cascode transistors in the output, the proposed structure remains approximately constant in a relatively large output voltage swing causing an invariable gain. To evaluate the proposed method an op amp was designed in 0.18μm CMOS technology. The simulation results showed a gain of 84dB, unity gain bandwidth of 12.45MHz and phase margin of 81 degree; with 1V power supply and 1pF load capacitor.

A 0.4 V Bulk-Driven Amplifier for Low-Power Data Converter Applications

This paper presents the design of an ultra low-voltage (ULV) pseudo operational transconductance amplifier (P-OTA) that is able to operate with a single supply voltage as low as 0.4 V. The proposed circuit is based on the bulk-driven technique and use of cross-coupled self-cascode pairs that boosts the differential DC gain. The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator. This expression for stability condition yield optimized value for the DC gain. Also, as the principle of operation of the proposed technique relies on matching conditions, Monte Carlo analyzes are considered to study of the behavior of the proposed circuit against mismatches. The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 μW. Eventually, from the proposed P-OTA, a low-power Sample and Hold (S/H) circuit with sampling frequency of 10 KS/s has been designed and simulated. The correct functionality for this configuration is verified from –30℃ to 70℃. The simulated data presented is obtained using the HSPICE Environment and is valid for the 90 nm triple-well CMOS process.

Ultra Low Power Improved Differential Amplifier

In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A d ), DC gain (A 0), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.

Rail-to-rail input/output operational transconductance amplifier (OTA) with high CMRR and PSRR

This paper introduces a low-voltage CMOS operational transconductance amplifier (OTA) with rail-to-rail input/output stages. Input stage uses floating gate transistors to realize rail-to-rail scheme. However, this scheme gives rise to reduction in transconductance of the OTA. To increase transconductance (G m), an effective partial positive feedback is used. Class AB output stage is so designed that improves the gain, slew rate, common mode rejection ratio and maximum swing of the OTA. With ±0.75 v power supply, this OTA consumes the low power of 397.5 μw. G m variation of input stage is 0.004% for rail-to-rail (±0.75 v) variation in common mode input signals and reaches to 0.036% beyond the rail-to-rail range (±1 v) which is a superior result compared with previously reported works. As is proved by theoretical relations and simulation results, proposed auxiliary circuit for rail-to-rail operation results in both high CMRR due to fixing common source node of input differential pair and high linearity due to attenuation of input signals. Simulation results show that CMRR in DC frequency is 259.5 dB and HD3 is −46 dB for 2.15 vP-P differential output voltage signal with applying a 0.48 vP-P input signal at 1 MHz. Proposed OTA is simulated in TSMC 0.18 μm CMOS technology with Hspice. Monte Carlo simulation results are included to forecast mismatch effects after fabrication process.