Abstract

In many applications, offset of the OP-AMPs should be canceled to high accuracy be accomplished. In this work, an asymmetrical differential input circuit with active DC offset rejection circuit was implemented to minimize the systematic offset of the amplifier. The proposed OP-AMPs show that the systematic offset voltages is less than 80 µV.

Highlights

  • The CMOS Op-Amp is an important building block of linear and switched-capacitor circuits

  • The systematic offset happens because of the channel length modulation of transistors and the value of the offset voltages are the functions of the input and output common mode voltages [1, 2, 3]

  • The systematic offset can be minimized by controlling bias current of input stage to sustain the input and output common mode in same level

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Summary

INTRODUCTION

The CMOS Op-Amp is an important building block of linear and switched-capacitor circuits. The channel length modulation is unimportant, with no feedback, the output common mode voltage ever shows the fixed voltage level and doesn’t follow the change of the input common mode voltage level. This difference between the input and output common mode level shows very small systematic offset voltages. The offset of VOUT is omitted when the switch 1 and 2 are turned off and the switch 3 and 4 are turned on This circuit has some disadvantages of large capacitor, and many CMOS switches which is the source of the switching error. A continuous time asymmetrical differential input circuit with common mode feedback circuit which can minimize the offset of OP-AMPs is presented

CIRCUIT DESCRIPTION
SIMULATION CIRCUIT
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