The Design and Optimization of Low-Voltage Pseudo Differential Pair Operational Transconductance Amplifier in 130 nm CMOS Technology

Abstract

This paper presents low-voltage pseudo differential pair operational transconductance amplifier (OTA) circuit designed and simulated in 130 nm CMOS technology. The imperialist competitive algorithm (ICA) is used to optimize the DC gain, common-mode rejection ratio (CMRR), and power dissipation of the presented OTA. The cost function of ICA is evaluated in the form of simulation-based rather than equation-based to increase the precision of the final results. The simulation results after optimization show that the proposed OTA has DC gain of 37.5 dB, CMRR of 37.5 dB, and maximum signal swing at the output of 210 mV, with power consumption of 200uW from power supply of 0.5V.