Low-voltage Differential Signaling Research Articles

Buried plastic scintillator muon telescope (BATATA)

Muon telescopes have multiple applications in the area of cosmic ray research. We are currently building such a detector with the objective of comparing the ground penetration of muon vs. electron-gamma signals originated in cosmic ray showers. The detector is composed by a set of three parallel dual-layer scintillator planes, buried at fixed depths ranging from 120 to 600 g / cm 2 . Each layer is 4 m 2 and is composed by 49 rectangular strips of 4 cm × 2 m , oriented at a 90 ∘ angle with respect to its companion layer, which gives an xy -coincidence pixel of 4 × 4 cm 2 . The scintillators are MINOS extruded polystyrene strips, with an embedded Bicron BC92 wavelength shifting (WLS) fibers, of 1.5 mm in diameter. Light is collected by Hamamatsu H7546B multi-anode PMTs of 64 pixels. The front-end (FE) electronics works in counting mode and signals are transmitted to the surface DAQ stage using low-voltage differential signaling (LVDS). Any strip signal above threshold opens a GPS-tagged 2 μ s data collection window. Data, including signal and background, are acquired by a system of FPGA (Spartan 2E) boards and a single-board computer (TS7800).

Design of an All-Digital LVDS Driver

This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-mum 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/bit.

Low-power LVDS I/O interface for above 2Gb/s-per-pin operation

Low Voltage Differential Signaling (LVDS) has become a popular choice for high-speed serial links to conquer the bandwidth bottleneck of intra-chip data transmission. This paper presents the design and the implementation of LVDS Input/Output (I/O) interface circuits in a standard 0.18 μm CMOS technology using thick gate oxide devices (3.3 V), fully compatible with LVDS standard. In the proposed transmitter, a novel Common-Mode FeedBack (CMFB) circuit is utilized to keep the common-mode output voltage stable over Process, supply Voltage and Temperature (PVT) variations. Because there are no area greedy resistors in the CMFB circuitry, the disadvantage of large die area in existing transmitter structures is avoided. To obtain sufficient gain, the receiver consists of three amplifying stages: a voltage amplifying stage, a transconductance amplifying stage, and a transimpedance amplifying stage. And to exclude inner nodes with high RC time constant, shunt-shunt negative feedback is introduced in the receiver. A novel active inductor shunt peaking structure is used in the receiver to fulfill the stringent requirements of high speed and wide Common-Mode Input Region (CMIR) without voltage gain, power dissipation and silicon area penalty. Simulation results show that data rates of 2 Gbps and 2.5 Gbps are achieved for the transmitter and receiver with power consumption of 13.2 mW and 8.3 mW respectively.

P‐40: EMI Reduction Technique by Differential Data Transmission through Lossless Modulo Coding

AbstractWe developed EMI (Electromagnetic Interference) reducing techniques which is based on vertically differential EMI suppression method by applying modulo reduction (MVDE) for lossless encoding to low voltage differential signal lines (LVDS). The frequency at peak field strength can be forecasted because the duty ratio of the MVDE signal and transition probability tends to become small. The quality of transmitted signal in MVDE is clarified by measuring the eye pattern of signal transmission. The novel technique reduces EMI by 12 dB for 32‐inch high‐definition TV monitor in displaying the H‐character image.

Reconfigurable RDMA communication framework of MULTI-DSP

The processing speed of the communication between nodes in a parallel processor has become the major bottleneck of the processor’s performance. RDMA (Remote Direct Memory Access) technology has drawn more attention recently due to its capability of transferring a larger amount of data, higher speed and reliability. 4DSP (4 Digital Signal Processing) module comprised of Tiger-SHARC201 chip is connected by LVDS (Low Voltage Differential Signal) circuits. This paper proposes a general and reconfigurable RDMA platform and its corresponding communication protocol with all the routes linked based on the zero copy. The protocol transfers message of DSP by interrupting of DMA and is applied on massive remote image impression, which reduces memory needs and working burden of CPU. The experiment results show this platform is efficient, flexible, and expandable of being integrated to a larger scale in the next development stages.

High-Frequency Thin-Film Transistor Circuits for System Displays

Thin-film transistor (TFT) circuits with unprecedented high-frequency performances were fabricated. Based on sub-micron TFTs on phase-modulated-eximer-laser-annealing (PMELA) crystallized silicon films, low-voltage-differential-signaling (LVDS) receivers and low-noise-amplifiers (LNAs) were fabricated. The LVDS receivers can handle a data rate as high as 800 Mbps, and the maximum power gain of the LNAs is 19.8 dB at 1.33 GHz.

A Slew Controlled LVDS Output Driver Circuit in 0.18 $\mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 mum CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 Omega resistor with an output voltage swing of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OD</sub> = 400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the measured output jitter is sigma <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> = 4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load RC time constant.

A Tree-Topology Multiplexer for Multiphase Clock System

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- mum CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation.

Implementation of local area network extension for instrumentation standard trigger capabilities in advanced data acquisition platforms

Synchronization mechanisms are an essential part of the real-time distributed data acquisition systems (DASs) used in fusion experiments. Traditionally, they have been based on the use of digital signals. The approach known as local area network extension for instrumentation (LXI) provides a set of very powerful synchronization and trigger mechanisms. The Intelligent Test Measurement System (ITMS) is a new platform designed to implement distributed data acquisition and fast data processing for fusion experiments. It is based on COMPATPCI technology and its extension to instrumentation (PXI). Hardware and software elements have been developed to include LXI trigger and synchronization mechanisms in this platform in order to obtain a class A LXI instrument. This paper describes the implementation of such a system, involving the following components: commercial hardware running a Linux operating system; a real-time extension to an operating system and network (RTAI and RTNET), which implements a software precision time protocol (PTP) using IEEE1588; an ad hoc PXI module to support hardware implementation of PTP-IEEE 1588; and the multipoint, low-voltage differential signaling hardware LXI trigger bus.

A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre- amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

Front-End ASIC for High Resolution X-Ray Spectrometers

We present an application specific integrated circuit (ASIC) for high-resolution X-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wire-bonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , dissipates 12 mW cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 degC on the 6 keV peak of a <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">55</sup> Fe source.

A low-noise current preamplifier in 120 nm CMOS technology

Abstract. In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS) based point-to-point data links or preamplifiers for photodetectors.

DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance

Some practical issues associated with enhancing the Cartesian impedance performance of flexible joint manipulator are investigated. A digital signal processing/field programmable gate array (DSP/FPGA) structure is proposed to realize the singular perturbation based impedance controller. To increase the bandwidth of torque control and minimize the joint torque ripple, boundary layer system and field-oriented control (FOC) are fully implemented in a FPGA of each joint. The kernel of the hardware system is a peripheral component interface (PCI)-based high speed floating-point DSP for the Cartesian level control, and FPGA for high speed (200 us cycle time) multipoint low-voltage differential signaling (M-LVDS) serial data bus communication between robot Cartesian level and joint level. Experimental results with a four-degree-of-freedom flexible-joint manipulator under constrained-motion task, demonstrate that the controller architecture can enhance the robot impedance performance effectively.

Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects

The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high performance, low power, and low area on wave-pipelined interconnect circuits. Based on this methodology, design optimizations for three different types of applications are performed and different design metrics are used to obtain the optimal values of supply voltage, number of repeaters, and interconnect dimensions for these applications. The optimal supply voltage for low-power applications is shown to be twice the threshold voltage. In addition, an optimal throughput-per-energy-area (TPEA) design is compared with low-voltage differential signaling (LVDS). The optimal TPEA design is shown to reduce dynamic power by 10% and wire area by 70% compared to LVDS, without any loss of throughput performance.

Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's

This paper proposes a dual-level low voltage differential signaling (DLVDS) circuit aimed at low power consumption and reducing transmission lines for LCD driver IC's. We apply two-bit binary data to the DLVDS circuit as inputs, and then the circuit converts these two inputs into two kinds of fully differential signal levels. In the DLVDS circuit, two transmission lines are sufficient to transfer two-bit binary inputs while keeping the conventional LVDS features. The receiver recovers the original two-bit binary data through a level decoding circuit. The proposed circuit was fabricated using a commercial 0.25μm CMOS technology. Under a 2.5V supply voltage, the circuit shows a data rate of 1-Gbps/2-line and power consumption of 35mW.

Flexible custom designs for CMS DAQ

The CMS central DAQ system is built using commercial hardware (PCs and networking equipment), except for two components: the Front-end Readout Link (FRL) and the Fast Merger Module (FMM). The FRL interfaces the sub-detector specific front-end electronics to the central DAQ system in a uniform way. The FRL is a compact-PCI module with an additional PCI 64bit connector to host a Network Interface Card (NIC). On the sub-detector side, the data are written to the link using a FIFO-like protocol (SLINK64). The link uses the Low Voltage Differential Signal (LVDS) technology to transfer data with a throughput of up to 400 MBytes/s. The FMM modules collect status signals from the front-end electronics of the sub-detectors, merge and monitor them and provide the resulting signals with low latency to the first level trigger electronics. In particular, the throttling signals allow the trigger to avoid buffer overflows and data corruption in the front-end electronics when the data produced in the front-end exceeds the capacity of the DAQ system. Both cards are compact-PCI cards with a 6U form factor. They are implemented with FPGAs. The main FPGA implements the processing logic of the card and the interfaces to the variety of busses on the card. Another FPGA contains a custom compact-PCI interface for configuration, control and monitoring. The chosen technology provides flexibility to implement new features if required.

ASIC for Small Angle Neutron Scattering Experiments at the SNS

We present an ASIC for a 3He gas detector to be used in small angle neutron scattering experiments at the spallation neutron source in oak ridge. The ASIC is composed of 64 channels with low noise charge amplification, filtering, timing and amplitude measurement circuits, where an innovative current-mode peak-detector and digitizer (PDAD) is adopted. The proposed PDAD provides at the same time peak detection and A/D conversion in real time, at low power, and without requiring a clock signal. The channels share an efficient data sparsification and derandomization scheme, a 30-bit 256 deep FIFO, and low voltage differential signaling.

P‐193: EMI Reducing Techniques for Low Voltage Differential Signaling by Applying a Vertically Differential Method and Data Arrangement Optimization

AbstractWe developed EMI (Electromagnetic Interference) reducing techniques that utilize a Vertically Differential EMI suppression method (VDE) and data arrangement optimization for Low Voltage Differential Signaling (LVDS) transmission lines. This method utilizes the vertical correlation of two adjacent horizontal lines for image data. It enables data signal frequencies below half of clock signal frequency and makes reverse phase between neighboring differential pair lines. The novel technique reduced EMI by 8 dB for a 20.8‐inch ultra‐high resolution monitor.

An Offset-Compensated LVDS Receiver with Low-Temperature Poly-Si Thin Film Transistor

The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly-Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.

Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels

This brief presents the design and implementation of a clock-and-data recovery (CDR) design for low-voltage differential signals (LVDS) transceiver operations. Instead of using an oversampling scheme which requires a high-speed clock generator, we adopt an interpolation scheme which relaxes the demand of a high-speed phase-locked loop with very high precision. A dual-tracking design is proposed to precisely align both edges of a data eye. Hence, the center of a data eye can be optimally sampled. A standard foundry 0.25-mum 1P5M CMOS technology is used to realize the proposed dual-tracking CDR for 7times100 (bit-MHz) LVDS signaling. The post-layout-extracted simulation reveals that the worst-case jitter of the sampling clocks is less than 450 ps (peak-to-peak) and 250 ps (rms) at all process corners